Purpose: Invalidity Analysis


Patent: US6618736B1
Filed: 2001-03-09
Issued: 2003-09-09
Patent Holder: (Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC
Inventor(s): Paul Menage

Title: Template-based creation and archival of file systems

Abstract: File systems are created and archived by providing a set of shared storage units and one or more templates, each template including a set of private storage units and a corresponding usage map.



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Non-Patent Literature        WIPO Prior Art        EP Prior Art        US Prior Art        CN Prior Art        JP Prior Art        KR Prior Art

GroundReferencesOwner of the ReferenceTitleSemantic MappingChallenged Claims
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1

IEEE JOURNAL OF SOLID-STATE CIRCUITS. 34 (4): 494-501 APR 1999

(Nakase, 1999)		Mitsubishi Electric Corporation, International Business Machines Corporation, Integrated Device Technology, Inc (IDT), Dynalog IncSource-synchronization And Timing Vernier Techniques For 1.2-GB/s SLDRAM Interface▪ storage unit writing module, storage units ≈ write operation, wait time
▪ second usage, second usage map ≈ data rate
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
2

ACM TRANSACTIONS ON COMPUTER SYSTEMS. 10 (1): 26-52 FEB 1992

(Rosenblum, 1992)		Stanford University, University of California, BerkeleyTHE DESIGN AND IMPLEMENTATION OF A LOG-STRUCTURED FILE SYSTEM▪ file systems ≈ file systems
▪ storage unit writing module ≈ free area
XXX
3

PROCEEDINGS OF THE 1999 IEEE SYMPOSIUM ON SECURITY AND PRIVACY. : 133-145 1999

(Warrender, 1999)		University of New MexicoDetecting Intrusions Using System Calls: Alternative Data Models▪ storage units ≈ different programs
▪ first set, second set ≈ data sets
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
4

COMPUTER. 26 (7): 8-16 JUL 1993

(Lee, 1993)		Bell Communications ResearchA FRAMEWORK FOR CONTROLLING COOPERATIVE AGENTS▪ local storage ≈ shared object
▪ first server ≈ shared data
XXXX
5

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS. E83D (4): 807-814 APR 2000

(Lee, 2000)		National Taipei College of NursingServer-based Maintenance Approach For Computer Classroom Workstations▪ file systems ≈ file systems
▪ storage unit, remote storage device ≈ hard disk
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
6

ACM TRANSACTIONS ON COMPUTER SYSTEMS. 15 (4): 412-447 NOV 1997

(Bugnion, 1997)		Stanford UniversityDisco: Running Commodity Operating Systems On Scalable Multiprocessors▪ storage unit writing module, computer program product ≈ system software
▪ program code ≈ program code
▪ file system ≈ file system
XXXXXX
7

JP2000298554A

(Shah Mohammed Rezaul Islam, 2000)		(Original Assignee) Internatl Business Mach Corp <Ibm>; インターナショナル・ビジネス・マシーンズ・コーポレ−ション     Ｒａｉｄデータ記憶システムにおける瞬時バックアップを提供する方法及びシステム▪ second set ≈ データ記憶システム
▪ second usage map ≈ エンジン
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
8

EP0927942A2

(Christopher J. Stakutis, 1999)		(Original Assignee) MERCURY COMPUTER SYSTEMS Inc     

(Current Assignee) MERCURY COMPUTER SYSTEMS Inc 		Methods and apparatus for high-speed access to and sharing of storage devices on a networked digital data processing system▪ storage unit writing module, storage unit update module ≈ parallel interface
▪ first server ≈ second request, first server
▪ data item ≈ storage device
XXXXXXXXXXXXXXXXXXXXXXXXXXXX
9

US6108759A

(Niel Orcutt, 2000)		(Original Assignee) Powerquest Corp     

(Current Assignee) Veritas Technologies LLC 		Manipulation of partitions holding advanced file systems▪ file system creation, file systems ≈ file system structure
▪ storage units, storage unit ≈ one disk, two disk
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
10

US5937159A

(William J. Meyers, 1999)		(Original Assignee) Data General Corp     

(Current Assignee) EMC Corp 		Secure computer system▪ archiving file systems ≈ authentication database
▪ storage units ≈ system administrator
▪ first set ≈ different one, first set
▪ second set ≈ second set
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
11

US6192389B1

(Donald F. Ault, 2001)		(Original Assignee) International Business Machines Corp     

(Current Assignee) International Business Machines Corp 		Method and apparatus for transferring file descriptors in a multiprocess, multithreaded client/server system▪ data item ≈ storage device
▪ second server ≈ second server
▪ first server ≈ first server
XXXXXXXXXXXXXXXXXXXXXXXX
12

CN1162786A

(沼尻裕, 1997)		(Original Assignee) 株式会社东芝     用于多任务设施信息处理系统的资源管理方法和设备▪ program code ≈ 计算机程序
▪ data item ≈ 理存储
XXXXXXXXXXXXXXXXXXXXXX
13

EP0759592A2

(Steven T. Senator, 1997)		(Original Assignee) Sun Microsystems Inc     

(Current Assignee) Sun Microsystems Inc 		System and method for file system lock and repair for a computer operating system▪ data item ≈ storage device
▪ file systems ≈ file systems
XXXXXXXXXXXXXXXXXXXXXX
14

US5918018A

(Mark P. Gooderum, 1999)		(Original Assignee) Secure Computing LLC     

(Current Assignee) McAfee LLC 		System and method for achieving network separation▪ first usage ≈ receiving information
▪ third set ≈ data objects
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
15

EP0715250A2

(Takahiro c/o NEC Corporation Okonogi, 1996)		(Original Assignee) NEC Corp     

(Current Assignee) NEC Corp 		Method of processing input/output request in computer system including a plurality of subsystems▪ data item ≈ storage device
▪ second server ≈ second access
▪ file system ≈ file system
▪ archiving file systems ≈ local input
▪ storage unit, corresponding storage unit ≈ one file
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
16

EP0709843A2

(Tsutomu c/o Intellectual Property Div Yamamoto, 1996)		(Original Assignee) Sony Corp     

(Current Assignee) Sony Corp 		Method, apparatus and medium for data recording and processing▪ file system creation ≈ management data, link data
▪ file systems, file system ≈ data recording
▪ computer program product ≈ first method
XXXXXXXXXXX
17

US5636371A

(Kin C. Yu, 1997)		(Original Assignee) Bull HN Information Systems Inc     

(Current Assignee) Bull HN Information Systems Inc 		Virtual network mechanism to access well known port application programs running on a single host system▪ storage unit update module ≈ first structure
▪ first server, first set ≈ first mapping, second mapping
XXXXXXXXXXXXXXXXXXXXXXXXXXX
18

US5706504A

(Robert G. Atkinson, 1998)		(Original Assignee) Microsoft Corp     

(Current Assignee) Microsoft Technology Licensing LLC 		Method and system for storing data objects using a small object data stream▪ storage unit ≈ storing objects
▪ first set ≈ defined size
▪ file system ≈ file system
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
19

US5715441A

(Robert G. Atkinson, 1998)		(Original Assignee) Microsoft Corp     

(Current Assignee) Microsoft Technology Licensing LLC 		Method and system for storing and accessing data in a compound document using object linking▪ first set ≈ different application
▪ storage unit ≈ storing objects
▪ file system ≈ file system
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
20

EP0683452A1

(Thomas R. Engelmann, 1995)		(Original Assignee) International Business Machines Corp     

(Current Assignee) International Business Machines Corp 		Partitioned log-structured file system and methods for operating same▪ file system ≈ said first part, file system
▪ storage units, storage unit ≈ one disk
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
21

EP0701716A1

(David Hitz, 1996)		(Original Assignee) NETWORK APPLIANCE Corp     

(Current Assignee) NETWORK APPLIANCE CORPORATION 		A method for allocating files in a file system integrated with a raid disk sub-system▪ file system ≈ file system
▪ archival module ≈ RAID array
XXXXXX
22

US5442765A

(Shoji Shiga, 1995)		(Original Assignee) NEC Corp     

(Current Assignee) NEC Corp 		Database system which adjusts the data storage order based on the processing speed of the storage media▪ merging module ≈ processing speeds
▪ corresponding storage unit ≈ controlling means
XXXXXXXXXXXXXXXXXXXXXX
23

US5212786A

(Kitty Sathi, 1993)		(Original Assignee) Xerox Corp     

(Current Assignee) Xerox Corp 		File compaction process for electronic printing systems▪ corresponding storage unit, storage units ≈ controlling means, one disk
▪ first set, second sets ≈ second sets, first set
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
24

US5088026A

(Gerald P. Bozman, 1992)		(Original Assignee) International Business Machines Corp     

(Current Assignee) International Business Machines Corp 		Method for managing a data cache using virtual external storage addresses as arguments▪ storage unit, storage unit reading module ≈ nonvolatile cache
▪ file system ≈ external storage
▪ computer program product ≈ second page
▪ file system creation ≈ d line
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
25

US5226160A

(James J. Waldron, 1993)		(Original Assignee) Visage Inc     

(Current Assignee) Visage Inc 		Method of and system for interactive video-audio-computer open architecture operation▪ storage unit writing module, computer program product ≈ system software
▪ storage unit update module, corresponding storage unit ≈ device manager
▪ first usage ≈ time t
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
26

JP2000348490A

(Hiroshi Takeda, 2000)		(Original Assignee) Hitachi Ltd; 株式会社日立製作所     メモリ装置▪ computer program product ≈ バーストモード
▪ first set, second set ≈ アップ
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
27

EP1039387A2

(Kouji c/o Hitachi Ltd Arai, 2000)		(Original Assignee) Hitachi Ltd     

(Current Assignee) Hitachi Ltd 		System and method for replicating data▪ computer program product ≈ computer program product
▪ local storage, storage units ≈ volume identifier
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
28

JP2001014257A

(Toshiaki Mizukami, 2001)		(Original Assignee) Kubota Corp; 株式会社クボタ     情報記録媒体交換装置及び情報記録媒体管理システム▪ data item ≈ 格納機構
▪ remote storage device ≈ ユニット
XXXXXXXXXXXXXXXXXXXXXXXXX
29

JPH11327991A

(Rajeev Rastogi, 1999)		(Original Assignee) Lucent Technol Inc; ルーセント テクノロジーズ インコーポレイテッド     ホットスペアシステムおよびデ―タベ―ス管理システム▪ storage unit, local storage device ≈ 少なくとも
▪ third set ≈ パラメータ
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
30

JP2000259583A

(Yasuyuki Ajimatsu, 2000)		(Original Assignee) Hitachi Ltd; 株式会社日立製作所     計算機システム▪ second server ≈ 管理テーブル
▪ storage unit, local storage device ≈ 少なくとも
▪ first set, second set ≈ アップ
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
31

WO9941667A1

(Thomas J. Holman, 1999)		(Original Assignee) Intel Corporation     Memory module including a memory module controller▪ corresponding storage units ≈ nonvolatile memory device
▪ merging module ≈ write transaction
▪ first server ≈ second number
▪ first set ≈ first number
▪ second usage, second usage map ≈ data rate
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
32

JP2000174505A

(Kanji Otsuka, 2000)		(Original Assignee) Fujitsu Ltd; Hitachi Ltd; Matsushita Electronics Industry Corp; Mitsubishi Electric Corp; Nec Corp; Oki Electric Ind Co Ltd; Kanji Otsuka; Rohm Co Ltd; Sanyo Electric Co Ltd; Sharp Corp; Sony Corp; Toshiba Corp; Tamotsu Usami; シャープ株式会社; ソニー株式会社; ローム株式会社; 三洋電機株式会社; 三菱電機株式会社; 寛治 大塚; 保 宇佐美; 富士通株式会社; 日本電気株式会社; 松下電子工業株式会社; 株式会社日立製作所; 株式会社東芝; 沖電気工業株式会社     電子装置▪ file system creation ≈ 受け取ること
▪ second set, second usage ≈ 有する第１
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
33

WO9912098A1

(Stephen Gold, 1999)		(Original Assignee) Hewlett-Packard Company     Data backup and recovery systems▪ first usage, first usage map ≈ non-volatile memory, time t
▪ archiving file systems ≈ secondary data
XXXXXXXXXXXXXXXXXXXXXXXXXXX
34

EP0884732A2

(Hisakatsu Araki, 1998)		(Original Assignee) Fujitsu Ltd     

(Current Assignee) Fujitsu Ltd 		Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system▪ storage unit writing module, corresponding storage unit ≈ voltage conversion circuit, current signals
▪ first set ≈ semiconductor chip, common value
▪ corresponding storage units ≈ latch circuits
▪ remote storage device ≈ input signals
▪ third set ≈ value v
▪ first usage ≈ time t
▪ file system creation ≈ d line
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
35

US6173377B1

(Moshe Yanai, 2001)		(Original Assignee) EMC Corp     

(Current Assignee) EMC Corp 		Remote data mirroring▪ file systems ≈ secondary storage device
▪ remote storage device ≈ background task
▪ archiving file systems ≈ secondary data
▪ second set ≈ second set
▪ first set ≈ first set
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
36

US6026414A

(Matthew Joseph Anglin, 2000)		(Original Assignee) International Business Machines Corp     

(Current Assignee) International Business Machines Corp 		System including a proxy client to backup files in a distributed computing environment▪ storage unit reading module, storage unit update module ≈ provides access
▪ data item ≈ storage device
▪ file system ≈ file system
XXXXXXXXXXXXXXXXXXXXXXXXX
37

EP0858031A1

(Viktors Berstis, 1998)		(Original Assignee) International Business Machines Corp     

(Current Assignee) International Business Machines Corp 		Alternate boot record▪ computer program product ≈ computer program product
▪ file system ≈ said first part
▪ file systems ≈ native system, system error
XXXXXX
38

US6076148A

(Nadav Kedem, 2000)		(Original Assignee) EMC Corp     

(Current Assignee) EMC Corp 		Mass storage subsystem and backup arrangement for digital data processing system which permits information to be backed up while host computer(s) continue(s) operating in connection with information stored on mass storage subsystem▪ first usage ≈ receiving information
▪ storage unit reading module ≈ one track
XXXXXXXXXXXXXXXXXXXXXXXXXXX
39

EP0845906A2

(Ashok Kakkunje Adiga, 1998)		(Original Assignee) International Business Machines Corp     

(Current Assignee) International Business Machines Corp 		Shared loop audio/video server system▪ data item ≈ storage device
▪ computer program product ≈ accessed data
▪ second set ≈ said server
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
40

EP0859308A1

(Yoshinori Terao, 1998)		(Original Assignee) Fujitsu Ltd     

(Current Assignee) Fujitsu Ltd 		Library control device for logically dividing and controlling library device and method thereof▪ computer program product ≈ readable recording medium
▪ corresponding storage unit ≈ controlling means
XXXXXXXXXXXXXXXXXXXX
41

US6021415A

(David Maxwell Cannon, 2000)		(Original Assignee) International Business Machines Corp     

(Current Assignee) HGST Netherlands BV 		Storage management system with file aggregation and space reclamation within aggregated files▪ second usage map ≈ available storage space
▪ storage unit ≈ processing apparatus, storage unit
▪ computer program product ≈ digital processing
▪ data item ≈ storage device
▪ second set ≈ including one
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
42

WO9815897A1

(Hans A. Wiggers, 1998)		(Original Assignee) Hewlett-Packard Company     Memory system and device▪ first server ≈ second number, shared data
▪ first usage, first usage map ≈ other memory, time t
▪ program code ≈ data word
XXXXXXXXXXXXXXXXXXXXXXXXXXX
43

JPH1173311A

(Robb David, 1999)		(Original Assignee) Vercon Ltd; バーコン リミテッド     コンピュータ・システムにおける記憶媒体に記憶された情報のアクセス及び変更を制御する方法及び装置▪ file systems, file system ≈ フォーマット
▪ storage unit, local storage device ≈ 少なくとも
▪ first set, second set ≈ アップ, エリア
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
44

US5887134A

(Zahir Ebrahim, 1999)		(Original Assignee) Sun Microsystems Inc     

(Current Assignee) Oracle America Inc 		System and method for preserving message order while employing both programmed I/O and DMA operations▪ storage units ≈ same destination node
▪ storage unit writing module ≈ first subset
XXXXXXXXXXXXXXXXXXXXXXXXXXX
45

US5905990A

(Scott D. Inglett, 1999)		(Original Assignee) International Business Machines Corp     

(Current Assignee) Seagate Systems UK Ltd 		File system viewpath mechanism▪ computer program product ≈ intermediate data
▪ data item ≈ storage device
▪ first set, second sets ≈ second sets, first set
▪ third set ≈ third set
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
46

US5844855A

(Frederick A. Ware, 1998)		(Original Assignee) Rambus Inc     

(Current Assignee) Rambus Inc 		Method and apparatus for writing to memory components▪ storage unit update module ≈ positive integer
▪ storage unit writing module ≈ write operation
▪ computer program product ≈ first input
▪ first usage ≈ time t
XXXXXXXXXXXXXXXXXXXXXXXXXXXX
47

US5901327A

(Yuval Ofek, 1999)		(Original Assignee) EMC Corp     

(Current Assignee) EMC Corp 		Bundling of write data from channel commands in a command chain for transmission over a data link between data storage systems for remote data mirroring▪ storage unit writing module ≈ write operation
▪ data item ≈ storage device
XXXXXXXXXXXXXXXXXXXXXX
48

EP0800135A1

(Norman Jackson White, 1997)		(Original Assignee) Arendee Ltd     

(Current Assignee) Arendee Ltd 		Method and apparatus for controlling access to and corruption of information in computer systems▪ file system creation ≈ updated information
▪ storage unit writing module, storage unit ≈ write operation, floppy disk
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
49

US5796624A

(Ramalingam Sridhar, 1998)		(Original Assignee) Research Foundation of State University of New York     

(Current Assignee) Research Foundation of State University of New York 		Method and apparatus for designing circuits for wave pipelining▪ computer program product ≈ first input
▪ second usage, second usage map ≈ high value
XXXXXXXXXXXXXXXXXXXXXXX
50

US5878408A

(Gary Alan Van Huben, 1999)		(Original Assignee) International Business Machines Corp     

(Current Assignee) International Business Machines Corp 		Data management system and process▪ computer program product ≈ first method
▪ first set, third set ≈ input file
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
51

US5835953A

(Richard Ohran, 1998)		(Original Assignee) Vinca Corp     

(Current Assignee) EMC Corp 		Backup system that takes a snapshot of the locations in a mass storage device that has been identified for updating prior to updating▪ file system creation, file system ≈ temporary storage means, consistent state
▪ storage unit, storage unit reading module ≈ stores data
▪ first usage ≈ time t
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
52

EP0767431A1

(John E. G. Matze, 1997)		(Original Assignee) STAC Inc     

(Current Assignee) STAC Inc 		System for backing up computer disk volumes▪ file system creation, file system ≈ temporary storage means
▪ second set, storage units ≈ following steps
▪ storage unit reading module, storage unit update module ≈ provides access
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
53

WO9712321A1

(Eva Chen, 1997)		(Original Assignee) Trend Micro, Incorporated     Virus detection and removal apparatus for computer networks▪ remote storage device, corresponding storage unit ≈ transferring data
▪ file systems, file system ≈ data files
XXXXXXXXXXXXXXXXXXXXXXXXXX
54

US5832515A

(Joel E. Ledain, 1998)		(Original Assignee) Veritas Software Corp     

(Current Assignee) Veritas Technologies LLC 		Log device layered transparently within a filesystem paradigm▪ first set, third set ≈ respective plurality
▪ file systems, archiving file systems ≈ data segments, ordered set
▪ file system creation, file system ≈ storage path
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
55

US5663661A

(John B. Dillon, 1997)		(Original Assignee) Rambus Inc     

(Current Assignee) Rambus Inc 		Modular bus with single or double parallel termination▪ corresponding storage unit, corresponding storage units ≈ current corresponding
▪ second set ≈ second set
▪ first set ≈ first set
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
56

WO9729413A2

(Mark P. Gooderum, 1997)		(Original Assignee) Secure Computing Corporation     System and method for achieving network separation▪ first usage ≈ receiving information
▪ third set ≈ data objects
▪ first set, second set ≈ first one
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
57

WO9631035A1

(Lynn R. Poliquin, 1996)		(Original Assignee) Cabletron Systems, Inc.     Method and apparatus for policy-based alarm notification in a distributed network management environment▪ second sets ≈ time interval
▪ file system creation ≈ called user
XXX
58

WO9716911A1

(Robert Cecil Gore, 1997)		(Original Assignee) International Business Machines Corporation; Ibm United Kingdom Limited     Secured gateway interface▪ corresponding storage unit ≈ second communication port
▪ program code ≈ program code
▪ second sets ≈ second pass, first pass
XXXXXXXXXXXXXXXXXXXXXX
59

EP0747829A1

(Ali Ezzet, 1996)		(Original Assignee) HP Inc     

(Current Assignee) HP Inc 		An input/output (I/O) processor providing shared resources for an I/O bus within a computer▪ remote storage device, corresponding storage unit ≈ transferring data
▪ data item ≈ temporary storage
▪ computer program product ≈ first input
XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
60

US5778419A

(Craig C. Hansen, 1998)		(Original Assignee) Microunity Systems Engineering Inc     

(Current Assignee) Microunity Systems Engineering Inc 		DRAM with high bandwidth interface that uses packets and arbitration▪ storage unit, storage unit reading module ≈ stores data
▪ program code ≈ data word
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
61

US5751997A

(Steven E. Kullick, 1998)		(Original Assignee) Apple Computer Inc     

(Current Assignee) Apple Inc 		Method and apparatus for transferring archival data among an arbitrarily large number of computer devices in a networked computer environment▪ remote storage device ≈ transferring data
▪ file system, file systems ≈ external storage, first backup
▪ second set ≈ including one
▪ second sets ≈ time interval
▪ corresponding storage unit, storage unit update module ≈ one disk, minimum time
▪ first usage ≈ time t
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
62

US5765173A

(David Cane, 1998)		(Original Assignee) Connected Corp     

(Current Assignee) Autonomy Inc 		High performance backup via selective file saving which can perform incremental backups and exclude files and uses a changed block signature list▪ storage units, corresponding storage units ≈ data areas
▪ storage unit, corresponding storage unit ≈ one file
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
63

JPH09185465A

(Kazuhiko Inoue, 1997)		(Original Assignee) Fujitsu Ltd; 富士通株式会社     ライブラリ装置、及び、情報処理システム、及び、制御モジュール▪ archival module, interception module ≈ 制御モジュール
▪ remote storage device ≈ ユニット
XXXXXXXXXXXXX
64

US5729743A

(Mark Squibb, 1998)		(Original Assignee) DeltaTech Res Inc     

(Current Assignee) DOUBLE-TAKE SOFTWARE CANADA Inc ; DeltaTech Res Inc 		Computer apparatus and method for merging system deltas▪ computer program product ≈ recorded data
▪ first usage ≈ time t
XXXXXXXXXXXXXXXXXXXXXXXXXX
65

US5778395A

(Douglas L. Whiting, 1998)		(Original Assignee) STAC Inc     

(Current Assignee) Veritas Technologies LLC 		System for backing up files from disk volumes on multiple nodes of a computer network▪ third set ≈ compression algorithm
▪ second set, storage units ≈ following steps
▪ corresponding storage unit, corresponding storage units ≈ function value
▪ file system, file systems ≈ file system, data files
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
66

US5748914A

(Richard Maurice Barth, 1998)		(Original Assignee) Rambus Inc     

(Current Assignee) Rambus Inc 		Protocol for communication with dynamic memory▪ corresponding storage unit ≈ transmitting control information
▪ second set, storage units ≈ following steps
▪ remote storage device ≈ first location
▪ first set ≈ more memory
▪ first usage ≈ time t
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
67

WO9613113A1

(William E. Boebert, 1996)		(Original Assignee) Secure Computing Corporation     System and method for providing secure internetwork services▪ remote storage device, corresponding storage unit ≈ transferring data
▪ interception module ≈ limiting access
▪ second set ≈ access rights
▪ file systems ≈ kernel code
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
68

US5907672A

(John E. G. Matze, 1999)		(Original Assignee) STAC Inc     

(Current Assignee) Veritas Technologies LLC 		System for backing up computer disk volumes with error remapping of flawed memory addresses▪ file system creation, file system ≈ temporary storage means
▪ second set, storage units ≈ following steps
▪ storage unit reading module, storage unit update module ≈ provides access
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
69

US5764963A

(Frederick Abbott Ware, 1998)		(Original Assignee) Rambus Inc     

(Current Assignee) Rambus Inc 		Method and apparatus for performing maskable multiple color block writes▪ storage unit writing module ≈ Memory apparatus
▪ second set, storage units ≈ following steps
▪ first usage map, second usage map ≈ memory block
▪ program code ≈ write signal
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
70

US5619644A

(Robert N. Crockett, 1997)		(Original Assignee) International Business Machines Corp     

(Current Assignee) International Business Machines Corp 		Software directed microcode state save for distributed storage controller▪ data item ≈ storage device
▪ archiving file systems ≈ secondary data
▪ second set ≈ including one
▪ file systems ≈ system error
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
71

JPH08227394A

(Fu-Chien Hsu, 1996)		(Original Assignee) Monolithic Syst Technol Inc; モノリシック・システム・テクノロジー・インコーポレイテッド     データ処理システム及びその動作方法▪ storage unit, local storage device ≈ 少なくとも
▪ second set ≈ インタリー
▪ data item ≈ シーケンス
▪ second sets, third set ≈ １セット
▪ storage unit reading module ≈ 前記前記
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
72

US5560000A

(Wilbur C. Vogley, 1996)		(Original Assignee) Texas Instruments Inc     

(Current Assignee) Texas Instruments Inc 		Time skewing arrangement for operating memory in synchronism with a data processor▪ storage unit writing module ≈ write operation
▪ first usage ≈ time t
XXXXXXXXXXXXXXXXXXXXXXXXXXX
73

US5615358A

(Wilbur C. Vogley, 1997)		(Original Assignee) Texas Instruments Inc     

(Current Assignee) Texas Instruments Inc 		Time skewing arrangement for operating memory in synchronism with a data processor▪ data item ≈ storage device
▪ first set ≈ different one
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
74

US5604862A

(Christopher W. Midgely, 1997)		(Original Assignee) Network Integrity Inc     

(Current Assignee) Autonomy Inc 		Continuously-snapshotted protection of computer files▪ first set ≈ current versions
▪ data item ≈ storage device
▪ second sets ≈ minimum set
▪ third set ≈ file server
▪ file system ≈ file system
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
75

JPH08202653A

(Toshiharu Murai, 1996)		(Original Assignee) Ricoh Co Ltd; 株式会社リコー     並列信号伝送装置▪ storage unit, local storage device ≈ 少なくとも
▪ storage units, corresponding storage units ≈ 繰り返し
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
76

US5649152A

(Richard S. Ohran, 1997)		(Original Assignee) Vinca Corp     

(Current Assignee) EMC Corp 		Method and system for providing a static snapshot of data stored on a mass storage system▪ second set, storage units ≈ following steps
▪ third set ≈ file server
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
77

US5422858A

(Masao Mizukami, 1995)		(Original Assignee) Hitachi ULSI Engineering Corp; Hitachi Ltd     

(Current Assignee) Hitachi ULSI Engineering Corp ; Renesas Electronics Corp 		Semiconductor integrated circuit▪ storage unit writing module ≈ write operation
▪ program code ≈ write signal
▪ remote storage device ≈ read gate
XXXXXX
78

US5444667A

(Takashi Obara, 1995)		(Original Assignee) NEC Corp     

(Current Assignee) Renesas Electronics Corp 		Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to allow timing generator to latch command signals▪ computer program product ≈ first input
▪ first set, second set ≈ first one
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
79

US5430676A

(Frederick A. Ware, 1995)		(Original Assignee) Rambus Inc     

(Current Assignee) Rambus Inc 		Dynamic random access memory system▪ first usage ≈ receiving information
▪ storage unit writing module ≈ write operation
XXXXXXXXXXXXXXXXXXXXXXX
80

US5404338A

(Yasumitsu Murai, 1995)		(Original Assignee) Mitsubishi Electric Engineering Co Ltd; Mitsubishi Electric Corp     

(Current Assignee) Mitsubishi Electric Corp 		Synchronous type semiconductor memory device operating in synchronization with an external clock signal▪ first set ≈ second connecting means, selected word line
▪ remote storage device ≈ instruction signal
▪ file systems, program code ≈ determined order
▪ file system creation, file system ≈ read data bus
▪ storage unit, storage unit update module ≈ counter means, row direction
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
81

US5390149A

(Wilbur C. Vogley, 1995)		(Original Assignee) Texas Instruments Inc     

(Current Assignee) Texas Instruments Inc 		System including a data processor, a synchronous dram, a peripheral device, and a system clock▪ second set ≈ second set
▪ file system creation ≈ d line
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
82

US5530623A

(Ikuo J. Sanwo, 1996)		(Original Assignee) NCR Corp     

(Current Assignee) Intellectual Ventures I LLC 		High speed memory packaging scheme▪ first set, third set ≈ respective point, more memory
▪ second sets ≈ common set
▪ storage unit ≈ two rows
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
83

US5495607A

(Thomas Pisello, 1996)		(Original Assignee) Seagate Peripherals Inc     

(Current Assignee) Clouding Corp 		Network management system having virtual catalog overview of files distributively stored across network domain▪ storage units ≈ nonvolatile data storage device
▪ program code ≈ checking means
▪ file systems, file system ≈ stored files, data files
XXXXXXXXXXXXXXXXXXXXXXXXXXXX
84

US5504873A

(Charles W. Martin, 1996)		(Original Assignee) E Systems Inc     

(Current Assignee) Raytheon Co 		Mass data storage and retrieval system▪ remote storage device ≈ read information
▪ second set ≈ second command
▪ second server ≈ second access
▪ file systems ≈ enable access
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
85

US5386375A

(Roger A. Smith, 1995)		(Original Assignee) Motorola Solutions Inc     

(Current Assignee) Motorola Solutions Inc 		Floating point data processor and a method for performing a floating point square root operation within the data processor▪ storage unit update module ≈ positive integer
▪ data item ≈ storage device
▪ third set ≈ value v
XXXXXXXXXXXXXXXXXXXXXX
86

US5428389A

(Kenji Ito, 1995)		(Original Assignee) Fuji Photo Film Co Ltd     

(Current Assignee) Fujifilm Corp 		Image data storage/processing apparatus▪ storage unit ≈ processing apparatus
▪ first server ≈ first pixel
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
87

US5329484A

(Hideo Tsuiki, 1994)		(Original Assignee) NEC Corp     

(Current Assignee) NEC Corp 		Semiconductor memory circuit, semiconductor memory module using the same, and acoustic signal reproducing system▪ first set, second set ≈ first one
▪ storage unit reading module, storage unit update module ≈ two data
XXXXXXXXXXXXXXXXXXXXXX
88

US5392239A

(Neal D. Margulis, 1995)		(Original Assignee) S3 Inc     

(Current Assignee) Samsung Electronics Co Ltd 		Burst-mode DRAM▪ computer program product ≈ digital storage
▪ storage unit writing module ≈ memory circuit
▪ second set ≈ second set
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
89

US5544347A

(Moshe Yanai, 1996)		(Original Assignee) EMC Corp     

(Current Assignee) EMC Corp 		Data storage system controlled remote data mirroring with respectively maintained data indices▪ data item ≈ storage device
▪ remote storage device ≈ first location
▪ archiving file systems ≈ secondary data
XXXXXXXXXXXXXXXXXXXXXXXXX
90

US5384745A

(Yasuhiro Konishi, 1995)		(Original Assignee) Mitsubishi Electric Corp     

(Current Assignee) Mitsubishi Electric Corp 		Synchronous semiconductor memory device▪ storage unit writing module ≈ reading operation, write operation
▪ file systems, program code ≈ determined order
▪ file system creation ≈ d line
XXXXX
91

US5323358A

(Haruki Toda, 1994)		(Original Assignee) Toshiba Corp     

(Current Assignee) Toshiba Corp 		Clock-synchronous semiconductor memory device and method for accessing the device▪ second usage ≈ external sources
▪ storage unit update module ≈ positive integer
▪ computer program product ≈ accessed data
▪ data item ≈ data items
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
92

US5381376A

(Min-Tae Kim, 1995)		(Original Assignee) Samsung Electronics Co Ltd     

(Current Assignee) Samsung Electronics Co Ltd 		Video RAM having block selection function during serial write transfer operation▪ remote storage device, corresponding storage unit ≈ transferring data
▪ storage unit writing module ≈ write operation
▪ first set ≈ different one
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
93

US5404463A

(James E. McGarvey, 1995)		(Original Assignee) Eastman Kodak Co     

(Current Assignee) Eastman Kodak Co 		Method and apparatus for transferring data in portable image processing system▪ first usage, first usage map ≈ other memory
▪ storage unit reading module, storage unit update module ≈ second diode
XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
94

US5319755A

(Michael Farmwald, 1994)		(Original Assignee) Rambus Inc     

(Current Assignee) Rambus Inc 		Integrated circuit I/O using high performance bus interface▪ storage unit ≈ approximately two, plane orthogonal
▪ storage unit writing module ≈ write operation
▪ second server ≈ second access
▪ usage map updating module ≈ lower voltage
▪ first usage ≈ time t
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
95

US5403639A

(Jay S. Belsan, 1995)		(Original Assignee) Oracle StorageTek     

(Current Assignee) Oracle StorageTek 		File server having snapshot application data groups▪ storage unit update module ≈ positive integer
▪ second sets ≈ identified set
▪ data item ≈ storage device
▪ second set ≈ second set
▪ first set ≈ first set
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
96

US5365489A

(Seong-ouk Jeong, 1994)		(Original Assignee) Samsung Electronics Co Ltd     

(Current Assignee) Samsung Electronics Co Ltd 		Dual port video random access memory with block write capability▪ first usage map, second usage map ≈ memory block
▪ program code ≈ write signal
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
97

US5164916A

(Andrew L. Wu, 1992)		(Original Assignee) Digital Equipment Corp     

(Current Assignee) Samsung Electronics Co Ltd 		High-density double-sided multi-string memory module with resistor for insertion detection▪ second set ≈ second set
▪ first set ≈ first set
▪ storage unit ≈ two rows
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
98

US5276858A

(Jayawant V. Oak, 1994)		(Original Assignee) Intel Corp     

(Current Assignee) Intel Corp 		Memory controller with integrated delay line circuitry▪ data item ≈ microprocessor function
▪ usage map updating module ≈ timing parameters
▪ first server ≈ second request
XXXXXXXXXXXXXXXXXXXXXXX
99

US5345573A

(Raymond D. Bowden, 1994)		(Original Assignee) Bull HN Information Systems Inc     

(Current Assignee) Bull HN Information Systems Inc 		High speed burst read address generation with high speed transfer▪ remote storage device, corresponding storage unit ≈ transferring data
▪ corresponding storage units ≈ latch circuits
▪ file system creation, file systems ≈ data sections
▪ first set ≈ different one, first number
▪ first server ≈ second number
▪ program code ≈ data word
XXXXX
100

US5124589A

(Toru Shiomi, 1992)		(Original Assignee) Mitsubishi Electric Corp     

(Current Assignee) Mitsubishi Electric Corp 		Semiconductor integrated circuit capable of synchronous and asynchronous operations and operating method therefor▪ second usage ≈ accessible memory
▪ corresponding storage units ≈ latch circuits
XXXXXXXXXXXXXXXXXXXXXX
101

WO9116680A1

(Michael Farmwald, 1991)		(Original Assignee) Rambus Inc.     Integrated circuit i/o using a high preformance bus interface▪ storage unit ≈ plane orthogonal
▪ storage unit writing module ≈ write operation
▪ first set, second set ≈ different one, more memory
▪ archiving file systems ≈ I/O interface
▪ first usage map, second usage map ≈ memory block
▪ second sets ≈ more lines
▪ first usage ≈ time t
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
102

US5379438A

(Alan G. Bell, 1995)		(Original Assignee) Xerox Corp     

(Current Assignee) Xerox Corp 		Transferring a processing unit's data between substrates in a parallel processor▪ remote storage device, corresponding storage unit ≈ transferring data
▪ storage unit update module ≈ transfer command
▪ first set, second set ≈ first one
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
103

US5117389A

(Tom D. H. Yiu, 1992)		(Original Assignee) Macronix International Co Ltd     

(Current Assignee) Macronix International Co Ltd 		Flat-cell read-only-memory integrated circuit▪ storage units ≈ storage units
▪ storage unit writing module ≈ first subset
▪ first set, second set ≈ first one
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
104

US5077693A

(Kim C. Hardee, 1991)		(Original Assignee) Motorola Solutions Inc     

(Current Assignee) Apple Inc ; NXP USA Inc 		Dynamic random access memory▪ first set ≈ selected word line
▪ program code ≈ write signal
XXXXXXXXXXXXXXXXXXXXXXXXXX
105

US5179687A

(Hideto Hidaka, 1993)		(Original Assignee) Mitsubishi Electric Corp     

(Current Assignee) Mitsubishi Electric Corp 		Semiconductor memory device containing a cache and an operation method thereof▪ second usage ≈ accessible memory
▪ computer program product ≈ data latches
XXXXXXXXXXXXXXXXXXXXXXX
106

US5111386A

(Kazuyasu Fujishima, 1992)		(Original Assignee) Mitsubishi Electric Corp     

(Current Assignee) Mitsubishi Electric Corp 		Cache contained type semiconductor memory device and operating method therefor▪ first usage, first usage map ≈ transfer gate transistors
▪ first set ≈ selected word line
▪ remote storage device, corresponding storage unit ≈ transferring data
▪ computer program product ≈ data latches
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
107

US5276867A

(Gregory Kenley, 1994)		(Original Assignee) Epoch Systems Inc     

(Current Assignee) Epoch Systems Inc 		Digital data storage system with improved data migration▪ second server ≈ client devices, second access
▪ file systems ≈ file systems
XX
108

US4937734A

(Andreas Bechtolsheim, 1990)		(Original Assignee) Sun Microsystems Inc     

(Current Assignee) Sun Microsystems Inc 		High speed bus with virtual memory data transfer and rerun cycle capability▪ remote storage device, corresponding storage unit ≈ transferring data
▪ file system creation ≈ d line
XXXXXXXXXXXXXXXXXXXXXXX
109

US5097489A

(Patrick A. Tucci, 1992)		(Original Assignee) National Semiconductor Corp     

(Current Assignee) National Semiconductor Corp 		Method for incorporating window strobe in a data synchronizer▪ corresponding storage unit ≈ controlling means
▪ computer program product ≈ first input
XXXXXXXXXXXXXXXXXXXX
110

US5001672A

(Timothy J. Ebbers, 1991)		(Original Assignee) International Business Machines Corp     

(Current Assignee) International Business Machines Corp 		Video ram with external select of active serial access register▪ remote storage device, corresponding storage unit ≈ transferring data
▪ storage unit, storage unit update module ≈ counter means
▪ first set ≈ different one
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		IEEE JOURNAL OF SOLID-STATE CIRCUITS. 34 (4): 494-501 APR 1999

Publication Year: 1999

Source-synchronization And Timing Vernier Techniques For 1.2-GB/s SLDRAM Interface

Mitsubishi Electric Corporation, International Business Machines Corporation, Integrated Device Technology, Inc (IDT), Dynalog Inc

Nakase, Morooka, Perlman, Kolor, Choi, Shin, Yoshimura, Watanabe, Matsuda, Kumanoya, Yamada
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units (write operation, wait time) and a second set of storage units , each storage unit (write operation, wait time) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (write operation, wait time) are stored in a same storage device . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (write operation, wait time) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (write operation, wait time) of the second set contains valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (write operation, wait time) of the second set contain valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (write operation, wait time) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (write operation, wait time) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (write operation, wait time) , each storage unit (write operation, wait time) of the third set corresponding to one of the storage units of the first set ;

providing a second usage (data rate) map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage (data rate) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (write operation, wait time) of the third set contains valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage (data rate) map comprises : initializing the second usage map to indicate that none of the storage units (write operation, wait time) of the third set contain valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (write operation, wait time) of the first set ;

and in response to the second usage (data rate) map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (write operation, wait time) of the first set ;

and in response to the second usage (data rate) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (write operation, wait time) of the first set ;

and in response to the second usage (data rate) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (write operation, wait time) of the second set for which an indication of valid data is stored in the first usage map . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units (write operation, wait time) with the third set of storage units . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (write operation, wait time) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (write operation, wait time) of the second set that is copied , storing an indication of valid data in the second usage (data rate) map . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (write operation, wait time) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (write operation, wait time) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units (write operation, wait time) and the first set of private storage units for the server . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (write operation, wait time) and the first usage map of a first server . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (write operation, wait time) are stored in a same storage device . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 22 . The method of claim 17 , wherein the shared storage units (write operation, wait time) are stored a local storage device and the private storage units are stored in a remote storage device . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (write operation, wait time) contains valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (write operation, wait time) contain valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (write operation, wait time) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (write operation, wait time) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units (write operation, wait time) , each private storage unit (write operation, wait time) of the second set corresponding to one of the shared storage units ;

providing a second usage (data rate) map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage (data rate) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (write operation, wait time) of the second set contains valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage (data rate) map comprises : initializing the second usage map to indicate that none of the private storage units (write operation, wait time) of the second set contain valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (write operation, wait time) ;

and in response to the second usage (data rate) map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (write operation, wait time) ;

and in response to the second usage (data rate) map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (write operation, wait time) ;

and in response to the second usage (data rate) map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (write operation, wait time) of the first set for which an indication of valid data is stored in the first usage map . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (write operation, wait time) with the second set of private storage units . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (write operation, wait time) of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (write operation, wait time) of the first set that is copied , storing an indication of valid data in the second usage (data rate) map . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate (second usage, second usage map) of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .

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CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units (write operation, wait time) and a second set of storage units , each storage unit (write operation, wait time) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (write operation, wait time) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		Source-synchronization And Timing Vernier Techniques For 1 . 2-GB/s SLDRAM Interface . This paper describes a validation system for an SLDRAM interface . The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style . The first technique is a source-synchronization scheme , Since the chip that transmits data also supplies the data clock , the clock and data are completely synchronous . The second is the timing vernier technique , A wait time (storage unit writing module, storage units, storage unit, storage unit update module) for output data is programmable in each SLDRAM . Therefore , the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size . The validation chip is designed to emulate these operations . The chip is fabricated using a 0 . 35-mu m CMOS process technology and packaged in a conventional 0 . 65-mm pitch thin small out-line package , mounted on a single-chip module , and put into an eight-module system . A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals . From system-level measurements , the data eye width of 600 ps is obtained at a data rate of 600 Mbps , Errorless data transmission is observed in both read and write operation (storage unit writing module, storage units, storage unit, storage unit update module) s in a bit-error rate testing . The validation system has successfully demonstrated a data-transmission rate of 1 . 2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2 . 5 V .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		ACM TRANSACTIONS ON COMPUTER SYSTEMS. 10 (1): 26-52 FEB 1992

Publication Year: 1992

THE DESIGN AND IMPLEMENTATION OF A LOG-STRUCTURED FILE SYSTEM

Stanford University, University of California, Berkeley

Rosenblum, Ousterhout
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CLAIM 17 . A method for creating and archiving file systems (file systems) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		THE DESIGN AND IMPLEMENTATION OF A LOG-STRUCTURED FILE SYSTEM . This paper presents a new technique for disk storage management called a log-structured file system . A log-structured file system writes all modifications to disk sequentially in a log-like structure , thereby speeding up both file writing and crash recovery . The log is the only structure on disk ;
it contains indexing information so that files can be read back from the log efficiently . In order to maintain large free areas on disk for fast writing , we divide the log into segments and use a segment cleaner to compress the live information from heavily fragmented segments . We present a series of simulations that demonstrate the efficiency of a simple cleaning policy based on cost and benefit . We have implemented a prototype log-structured file system called Sprite LFS ;
it outperforms current Unix file systems (file systems) by an order of magnitude for small-file writes while matching or exceeding Unix performance for reads and large writes . Even when the overhead for cleaning is included , Sprite LFS can use 70% of the disk bandwidth for writing , whereas Unix file systems typically can use only 5-10% .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (free area) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		THE DESIGN AND IMPLEMENTATION OF A LOG-STRUCTURED FILE SYSTEM . This paper presents a new technique for disk storage management called a log-structured file system . A log-structured file system writes all modifications to disk sequentially in a log-like structure , thereby speeding up both file writing and crash recovery . The log is the only structure on disk ;
it contains indexing information so that files can be read back from the log efficiently . In order to maintain large free area (storage unit writing module) s on disk for fast writing , we divide the log into segments and use a segment cleaner to compress the live information from heavily fragmented segments . We present a series of simulations that demonstrate the efficiency of a simple cleaning policy based on cost and benefit . We have implemented a prototype log-structured file system called Sprite LFS ;
it outperforms current Unix file systems by an order of magnitude for small-file writes while matching or exceeding Unix performance for reads and large writes . Even when the overhead for cleaning is included , Sprite LFS can use 70% of the disk bandwidth for writing , whereas Unix file systems typically can use only 5-10% .

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CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module (free area) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		THE DESIGN AND IMPLEMENTATION OF A LOG-STRUCTURED FILE SYSTEM . This paper presents a new technique for disk storage management called a log-structured file system . A log-structured file system writes all modifications to disk sequentially in a log-like structure , thereby speeding up both file writing and crash recovery . The log is the only structure on disk ;
it contains indexing information so that files can be read back from the log efficiently . In order to maintain large free area (storage unit writing module) s on disk for fast writing , we divide the log into segments and use a segment cleaner to compress the live information from heavily fragmented segments . We present a series of simulations that demonstrate the efficiency of a simple cleaning policy based on cost and benefit . We have implemented a prototype log-structured file system called Sprite LFS ;
it outperforms current Unix file systems by an order of magnitude for small-file writes while matching or exceeding Unix performance for reads and large writes . Even when the overhead for cleaning is included , Sprite LFS can use 70% of the disk bandwidth for writing , whereas Unix file systems typically can use only 5-10% .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		PROCEEDINGS OF THE 1999 IEEE SYMPOSIUM ON SECURITY AND PRIVACY. : 133-145 1999

Publication Year: 1999

Detecting Intrusions Using System Calls: Alternative Data Models

University of New Mexico

Warrender, Forrest, Pearlmutter, Ieee, Ieee, Ieee, Ieee
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (data sets) of storage units (different programs) and a second set (data sets) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

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CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (different programs) are stored in a same storage device . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (data sets) of storage units (different programs) is stored in a local storage device and the second set (data sets) of storage units is stored in a remote storage device . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (data sets) contains valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (different programs) of the second set (data sets) contain valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (data sets) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (data sets) contains valid data , reading the data item from the corresponding storage unit of the second set . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (data sets) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (data sets) does not contain valid data , reading the data item from the storage unit of the first set . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (different programs) , each storage unit of the third set corresponding to one of the storage units of the first set (data sets) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (different programs) of the third set contain valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (data sets) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (data sets) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (data sets) contains valid data , reading the data item from the corresponding storage unit of the second set . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (data sets) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (data sets) does not contain valid data , reading the data item from the storage unit of the first set . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (data sets) for which an indication of valid data is stored in the first usage map . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (data sets) of storage units (different programs) with the third set of storage units . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (different programs) of the second set (data sets) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (different programs) ;

for each of the plurality of servers : providing a first set (data sets) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units (different programs) and the first set (data sets) of private storage units for the server . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (data sets) of private storage units (different programs) and the first usage map of a first server . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (different programs) are stored in a same storage device . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (different programs) are stored a local storage device and the private storage units are stored in a remote storage device . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (different programs) contain valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (data sets) of private storage units (different programs) , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (data sets) contains valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (different programs) of the second set (data sets) contain valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (data sets) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (data sets) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (data sets) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (data sets) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (data sets) does not contain valid data , reading the data item from the shared storage unit . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (data sets) for which an indication of valid data is stored in the first usage map . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (data sets) of private storage units (different programs) with the second set (data sets) of private storage units . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (different programs) of the first set (data sets) that contain valid data to those corresponding private storage units of the second set (data sets) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (data sets) of storage units (different programs) and a second set (data sets) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (different programs) are stored in a same storage device . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (data sets) of storage units (different programs) is stored in a local storage device and the second set (data sets) of storage units is stored in a remote storage device . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (data sets) contains valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (different programs) of the second set (data sets) contain valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (data sets) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (data sets) contains valid data , to read the data item from the corresponding storage unit of the second set . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (data sets) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (data sets) does not contain valid data , to read the data item from the storage unit of the first set . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (different programs) , each storage unit of the third set corresponding to one of the storage units of the first set (data sets) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (data sets) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (different programs) of the third set contain valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (data sets) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (data sets) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (data sets) contains valid data , to read the data item from the corresponding storage unit of the second set . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (data sets) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (data sets) does not contain valid data , to read the data item from the storage unit of the first set . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

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CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (data sets) for which an indication of valid data is stored in the first usage map . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

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CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (data sets) of storage units (different programs) with the third set of storage units . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

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CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (different programs) of the second set (data sets) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .

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CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (data sets) of storage units (different programs) and a second set (data sets) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		Detecting Intrusions Using System Calls : Alternative Data Models . Intrusion detection systems rely on a wide variety of observable data to distinguish between legitimate and illegitimate activities . In this paper we study one such observable-sequences of system calls into the kernel of an operating system . Using system-call data sets (first set, second set) generated by several different programs (storage units) , we compare the ability of different data modeling methods to represent normal behavior accurately and to recognize intrusions . We compare the following methods : Simple enumeration of observed sequences , comparison of relative frequencies of different sequences , a rule induction technique , and Hidden Markov Models (HMMs) . We discuss the factors affecting the performance of each method , and conclude that for this particular problem , weaker methods than HMMs are likely sufficient .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		COMPUTER. 26 (7): 8-16 JUL 1993

Publication Year: 1993

A FRAMEWORK FOR CONTROLLING COOPERATIVE AGENTS

Bell Communications Research

Lee, Mansfield, Sheth
US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage (shared object) device and the second set of storage units is stored in a remote storage device . 		A FRAMEWORK FOR CONTROLLING COOPERATIVE AGENTS . It is a challenge to support advanced applications involving multiple users in a distributed computing environment that consists of heterogeneous and autonomous resources . A distributed cooperative task in which multiple agents cooperate to achieve application objectives offers flexible and reliable support . Controlling interactions among the cooperating agents is a critical issue in such a paradigm . The ITX (interactive transaction) system supports complex interactions among cooperating agents in the presence Of user interventions that change application objectives and system failures . ITX supports reliable operations on shared object (local storage) s (representing cooperative objectives , shared data structures , and resources) that are stored in heterogeneous and autonomous component systems . A novel application-independent criterion called fixed point defines a stable system state with respect to an agent . Agents achieve a fixed point and the application-dependent cooperative objective by using a feedback control strategy that involves iterative execution of ITXs . These ITXs consist of atomic transactions that manipulate the shared objects . The authors use a multimedia teleconferencing service to illustrate the important features and advantages of the ITX system .

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CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage map of a first server (shared data) . 		A FRAMEWORK FOR CONTROLLING COOPERATIVE AGENTS . It is a challenge to support advanced applications involving multiple users in a distributed computing environment that consists of heterogeneous and autonomous resources . A distributed cooperative task in which multiple agents cooperate to achieve application objectives offers flexible and reliable support . Controlling interactions among the cooperating agents is a critical issue in such a paradigm . The ITX (interactive transaction) system supports complex interactions among cooperating agents in the presence Of user interventions that change application objectives and system failures . ITX supports reliable operations on shared objects (representing cooperative objectives , shared data (first server) structures , and resources) that are stored in heterogeneous and autonomous component systems . A novel application-independent criterion called fixed point defines a stable system state with respect to an agent . Agents achieve a fixed point and the application-dependent cooperative objective by using a feedback control strategy that involves iterative execution of ITXs . These ITXs consist of atomic transactions that manipulate the shared objects . The authors use a multimedia teleconferencing service to illustrate the important features and advantages of the ITX system .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage (shared object) device and the private storage units are stored in a remote storage device . 		A FRAMEWORK FOR CONTROLLING COOPERATIVE AGENTS . It is a challenge to support advanced applications involving multiple users in a distributed computing environment that consists of heterogeneous and autonomous resources . A distributed cooperative task in which multiple agents cooperate to achieve application objectives offers flexible and reliable support . Controlling interactions among the cooperating agents is a critical issue in such a paradigm . The ITX (interactive transaction) system supports complex interactions among cooperating agents in the presence Of user interventions that change application objectives and system failures . ITX supports reliable operations on shared object (local storage) s (representing cooperative objectives , shared data structures , and resources) that are stored in heterogeneous and autonomous component systems . A novel application-independent criterion called fixed point defines a stable system state with respect to an agent . Agents achieve a fixed point and the application-dependent cooperative objective by using a feedback control strategy that involves iterative execution of ITXs . These ITXs consist of atomic transactions that manipulate the shared objects . The authors use a multimedia teleconferencing service to illustrate the important features and advantages of the ITX system .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage (shared object) device and the second set of storage units is stored in a remote storage device . 		A FRAMEWORK FOR CONTROLLING COOPERATIVE AGENTS . It is a challenge to support advanced applications involving multiple users in a distributed computing environment that consists of heterogeneous and autonomous resources . A distributed cooperative task in which multiple agents cooperate to achieve application objectives offers flexible and reliable support . Controlling interactions among the cooperating agents is a critical issue in such a paradigm . The ITX (interactive transaction) system supports complex interactions among cooperating agents in the presence Of user interventions that change application objectives and system failures . ITX supports reliable operations on shared object (local storage) s (representing cooperative objectives , shared data structures , and resources) that are stored in heterogeneous and autonomous component systems . A novel application-independent criterion called fixed point defines a stable system state with respect to an agent . Agents achieve a fixed point and the application-dependent cooperative objective by using a feedback control strategy that involves iterative execution of ITXs . These ITXs consist of atomic transactions that manipulate the shared objects . The authors use a multimedia teleconferencing service to illustrate the important features and advantages of the ITX system .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS. E83D (4): 807-814 APR 2000

Publication Year: 2000

Server-based Maintenance Approach For Computer Classroom Workstations

National Taipei College of Nursing

Lee
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit (hard disk) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (hard disk) . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (hard disk) of the second set contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (hard disk) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (hard disk) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (hard disk) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (hard disk) of the third set contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (hard disk) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (hard disk) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (hard disk) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (hard disk) of the second set for which an indication of valid data is stored in the first usage map . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (hard disk) of the second set that is copied , storing an indication of valid data in the second usage map . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (file systems) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (hard disk) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems (file systems) , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (hard disk) . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (hard disk) contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (hard disk) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (hard disk) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (hard disk) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (hard disk) of the second set contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (hard disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (hard disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (hard disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (hard disk) of the first set for which an indication of valid data is stored in the first usage map . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (hard disk) of the first set that is copied , storing an indication of valid data in the second usage map . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (hard disk) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (hard disk) . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (hard disk) of the second set contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (hard disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (hard disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (hard disk) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (hard disk) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (hard disk) of the third set contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (hard disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (hard disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (hard disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (hard disk) of the second set for which an indication of valid data is stored in the first usage map . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (hard disk) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (hard disk) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		Server-based Maintenance Approach For Computer Classroom Workstations . This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations . The approach takes several advantages : (1) applicable to the FAT (file allocation table) and NTFS file systems , (2) renovating all workstations to workable state , (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses , and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one . The basic concept of the server-based maintenance approach is to install whole software systems , including operating system and applications , on a normal workstation , to make one image copy of the workstation's hard disk (storage unit, remote storage device, storage unit writing module, storage unit update module) and store it onto network server , and to restore the image file from the server to the remaining workstations . In order to change computer name and IP automatically , this paper presents a searching heuristic for finding their locations in the image file . The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9% .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		ACM TRANSACTIONS ON COMPUTER SYSTEMS. 15 (4): 412-447 NOV 1997

Publication Year: 1997

Disco: Running Commodity Operating Systems On Scalable Multiprocessors

Stanford University

Bugnion, Devine, Govil, Rosenblum
US6618736B1
CLAIM 1 . A method for file system (file system) creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		Disco : Running Commodity Operating Systems On Scalable Multiprocessors . In this article we examine the problem of extending modern operating systems to run efficiently on large-scale shared-memory multiprocessors without a large implementation effort . Our approach brings back an idea popular in the 1970s : virtual machine monitors . We use virtual machines to run multiple commodity operating systems on a scalable multiprocessor . This solution addresses many of the challenges facing the system software for these machines . We demonstrate our approach with a prototype called Disco that runs multiple copies of Silicon Graphics' IRIX operating system on a multiprocessor . Our experience shows that the overheads of the monitor are small and that the approach provides scalability as well as the ability to deal with the nonuniform memory access time of these systems . To reduce the memory overheads associated with running multiple operating systems , virtual machines transparently share major data structures such as the program code and the file system (file system) buffer cache . We use the distributed-system support of modern operating systems to export a partial single system image to the users . The overall solution achieves most of the benefits of operating systems customized for scalable multiprocessors , yet it can be achieved with a significantly smaller implementation effort .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (file system) of each server comprises a combination of the set of shared storage units and the first set of private storage units for the server . 		Disco : Running Commodity Operating Systems On Scalable Multiprocessors . In this article we examine the problem of extending modern operating systems to run efficiently on large-scale shared-memory multiprocessors without a large implementation effort . Our approach brings back an idea popular in the 1970s : virtual machine monitors . We use virtual machines to run multiple commodity operating systems on a scalable multiprocessor . This solution addresses many of the challenges facing the system software for these machines . We demonstrate our approach with a prototype called Disco that runs multiple copies of Silicon Graphics' IRIX operating system on a multiprocessor . Our experience shows that the overheads of the monitor are small and that the approach provides scalability as well as the ability to deal with the nonuniform memory access time of these systems . To reduce the memory overheads associated with running multiple operating systems , virtual machines transparently share major data structures such as the program code and the file system (file system) buffer cache . We use the distributed-system support of modern operating systems to export a partial single system image to the users . The overall solution achieves most of the benefits of operating systems customized for scalable multiprocessors , yet it can be achieved with a significantly smaller implementation effort .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (file system) for a second server using the stored template . 		Disco : Running Commodity Operating Systems On Scalable Multiprocessors . In this article we examine the problem of extending modern operating systems to run efficiently on large-scale shared-memory multiprocessors without a large implementation effort . Our approach brings back an idea popular in the 1970s : virtual machine monitors . We use virtual machines to run multiple commodity operating systems on a scalable multiprocessor . This solution addresses many of the challenges facing the system software for these machines . We demonstrate our approach with a prototype called Disco that runs multiple copies of Silicon Graphics' IRIX operating system on a multiprocessor . Our experience shows that the overheads of the monitor are small and that the approach provides scalability as well as the ability to deal with the nonuniform memory access time of these systems . To reduce the memory overheads associated with running multiple operating systems , virtual machines transparently share major data structures such as the program code and the file system (file system) buffer cache . We use the distributed-system support of modern operating systems to export a partial single system image to the users . The overall solution achieves most of the benefits of operating systems customized for scalable multiprocessors , yet it can be achieved with a significantly smaller implementation effort .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (file system) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (system software) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		Disco : Running Commodity Operating Systems On Scalable Multiprocessors . In this article we examine the problem of extending modern operating systems to run efficiently on large-scale shared-memory multiprocessors without a large implementation effort . Our approach brings back an idea popular in the 1970s : virtual machine monitors . We use virtual machines to run multiple commodity operating systems on a scalable multiprocessor . This solution addresses many of the challenges facing the system software (storage unit writing module, computer program product) for these machines . We demonstrate our approach with a prototype called Disco that runs multiple copies of Silicon Graphics' IRIX operating system on a multiprocessor . Our experience shows that the overheads of the monitor are small and that the approach provides scalability as well as the ability to deal with the nonuniform memory access time of these systems . To reduce the memory overheads associated with running multiple operating systems , virtual machines transparently share major data structures such as the program code and the file system (file system) buffer cache . We use the distributed-system support of modern operating systems to export a partial single system image to the users . The overall solution achieves most of the benefits of operating systems customized for scalable multiprocessors , yet it can be achieved with a significantly smaller implementation effort .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module (system software) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		Disco : Running Commodity Operating Systems On Scalable Multiprocessors . In this article we examine the problem of extending modern operating systems to run efficiently on large-scale shared-memory multiprocessors without a large implementation effort . Our approach brings back an idea popular in the 1970s : virtual machine monitors . We use virtual machines to run multiple commodity operating systems on a scalable multiprocessor . This solution addresses many of the challenges facing the system software (storage unit writing module, computer program product) for these machines . We demonstrate our approach with a prototype called Disco that runs multiple copies of Silicon Graphics' IRIX operating system on a multiprocessor . Our experience shows that the overheads of the monitor are small and that the approach provides scalability as well as the ability to deal with the nonuniform memory access time of these systems . To reduce the memory overheads associated with running multiple operating systems , virtual machines transparently share major data structures such as the program code and the file system buffer cache . We use the distributed-system support of modern operating systems to export a partial single system image to the users . The overall solution achieves most of the benefits of operating systems customized for scalable multiprocessors , yet it can be achieved with a significantly smaller implementation effort .

US6618736B1
CLAIM 53 . An computer program product (system software) for creating and archiving a file system (file system) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code (program code) for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		Disco : Running Commodity Operating Systems On Scalable Multiprocessors . In this article we examine the problem of extending modern operating systems to run efficiently on large-scale shared-memory multiprocessors without a large implementation effort . Our approach brings back an idea popular in the 1970s : virtual machine monitors . We use virtual machines to run multiple commodity operating systems on a scalable multiprocessor . This solution addresses many of the challenges facing the system software (storage unit writing module, computer program product) for these machines . We demonstrate our approach with a prototype called Disco that runs multiple copies of Silicon Graphics' IRIX operating system on a multiprocessor . Our experience shows that the overheads of the monitor are small and that the approach provides scalability as well as the ability to deal with the nonuniform memory access time of these systems . To reduce the memory overheads associated with running multiple operating systems , virtual machines transparently share major data structures such as the program code (program code) and the file system (file system) buffer cache . We use the distributed-system support of modern operating systems to export a partial single system image to the users . The overall solution achieves most of the benefits of operating systems customized for scalable multiprocessors , yet it can be achieved with a significantly smaller implementation effort .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		JP2000298554A

Filed: 2000-03-22     Issued: 2000-10-24

Ｒａｉｄデータ記憶システムにおける瞬時バックアップを提供する方法及びシステム

(Original Assignee) Internatl Business Mach Corp <Ibm>; インターナショナル・ビジネス・マシーンズ・コーポレ−ション     

Shah Mohammed Rezaul Islam, Vikram H Krishnamurthy, Philip A Richardson, Prasenjit Sarkar, シャー・モハメッド・リゾール・イスラム, ビクラム・エイチ・クリシュナマシー, フィリップ・エイ・リチャードソン, プラゼンジット・サーカー
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set (データ記憶システム) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set (データ記憶システム) of storage units is stored in a remote storage device . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (データ記憶システム) contains valid data . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (データ記憶システム) contain valid data . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (データ記憶システム) contains valid data , reading the data item from the corresponding storage unit of the second set . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (データ記憶システム) does not contain valid data , reading the data item from the storage unit of the first set . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map (エンジン) for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map (エンジン) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map (エンジン) comprises : initializing the second usage map to indicate that none of the storage units of the third set contain valid data . 		JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map (エンジン) indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map (エンジン) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (データ記憶システム) contains valid data , reading the data item from the corresponding storage unit of the second set . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map (エンジン) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (データ記憶システム) does not contain valid data , reading the data item from the storage unit of the first set . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (データ記憶システム) for which an indication of valid data is stored in the first usage map . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (データ記憶システム) of storage units with the third set of storage units . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (データ記憶システム) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map (エンジン) . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (データ記憶システム) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map (エンジン) for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map (エンジン) comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (データ記憶システム) contains valid data . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map (エンジン) comprises : initializing the second usage map to indicate that none of the private storage units of the second set (データ記憶システム) contain valid data . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map (エンジン) indicating that the corresponding private storage unit of the second set (データ記憶システム) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map (エンジン) indicating that the corresponding private storage unit of the second set (データ記憶システム) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map (エンジン) indicating that the corresponding private storage unit of the second set (データ記憶システム) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units with the second set (データ記憶システム) of private storage units . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set (データ記憶システム) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map (エンジン) . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (データ記憶システム) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set (データ記憶システム) of storage units is stored in a remote storage device . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (データ記憶システム) contains valid data . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (データ記憶システム) contain valid data . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (データ記憶システム) contains valid data , to read the data item from the corresponding storage unit of the second set . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (データ記憶システム) does not contain valid data , to read the data item from the storage unit of the first set . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map (エンジン) for indicating which storage units of third set contain valid data . 		JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map (エンジン) that the corresponding storage unit of the third set contains valid data . 		JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map (エンジン) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map (エンジン) is initially reset to indicate that none of the storage units of the third set contain valid data . 		JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map (エンジン) indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map (エンジン) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (データ記憶システム) contains valid data , to read the data item from the corresponding storage unit of the second set . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map (エンジン) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (データ記憶システム) does not contain valid data , to read the data item from the storage unit of the first set . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (データ記憶システム) for which an indication of valid data is stored in the first usage map . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (データ記憶システム) of storage units with the third set of storage units . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。
US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (データ記憶システム) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map (エンジン) . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。

JP2000298554A
CLAIM 8 【請求項８】ＲＡＩＤデータ記憶システム内の複数のド ライブのソース・ドライブの一部のコピーを提供するシ ステムであって、前記ソース・ドライブの一部が複数の セグメントを含むものにおいて、 前記ソース・ドライブに関連付けられ、前記複数のセグ メントのコピーを記憶するターゲット・ドライブと、 前記ソース・ドライブ及び前記ターゲット・ドライブに 接続され、前記複数のセグメントのコピーを前記ターゲ ット・ドライブ上に提供するコピー・エンジン (second usage map) と、 前記コピー・エンジンに接続され、前記複数のセグメン トのコピーが前記ターゲット・ドライブに提供されたか 否かの指示を含むメタデータとを含み、前記コピー・エ ンジンが前記複数のセグメントのコピーを前記ターゲッ ト・ドライブに提供する間に、前記ソース・ドライブ及 び前記ターゲット・ドライブへの入出力を可能にする、 システム。
US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (データ記憶システム) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2000298554A
CLAIM 1 【請求項１】ＲＡＩＤデータ記憶システム (second set) 内の複数のド ライブのソース・ドライブの一部のコピーを提供する方 法であって、前記ソース・ドライブの一部が複数のセグ メントを含むものにおいて、 ａ）前記ソース・ドライブを前記複数のドライブのター ゲット・ドライブに関連付けるステップと、 ｂ）前記複数のセグメントのコピーを前記ターゲット・ ドライブ上に提供するステップとを含み、前記複数のセ グメントのコピーを提供するステップの間に、前記ソー ス・ドライブ及び前記ターゲット・ドライブへの入出力 を可能にする、方法。



US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0927942A2

Filed: 1998-09-02     Issued: 1999-07-07

Methods and apparatus for high-speed access to and sharing of storage devices on a networked digital data processing system

(Original Assignee) MERCURY COMPUTER SYSTEMS Inc     (Current Assignee) MERCURY COMPUTER SYSTEMS Inc

Christopher J. Stakutis, Kevin M. Stearns
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit (parallel interface) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (parallel interface) of the second set contains valid data . 		EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (parallel interface) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (parallel interface) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit (parallel interface) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (parallel interface) of the third set contains valid data . 		EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (parallel interface) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (parallel interface) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (parallel interface) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage map of a first server (second request, first server) . 		EP0927942A2
CLAIM 5 A digital data processing system according to claim 4 , wherein the first bypass at least initiates obtaining administrative information from the second node by generating and applying to the file system a second access request , the second request (first server) being for access to a logical unit to which access is controlled by the second node .

EP0927942A2
CLAIM 15 A scaleable networked digital data processing system with improved access to information stored on a first peripheral device , comprising A . a plurality of networked nodes , including at least first and second server nodes , coupled to one another via a first communications pathway , B . the second server node being coupled to a first peripheral device over a second communications pathway , C . the first server (first server) node being coupled to the first peripheral device over a third communications pathway , D . each of the first and second server nodes being coupled to zero , one or more client nodes , E . a file system , executing on at least the first and second server nodes , being capable of responding to access requests generated by the first server node , for (i) transferring data designated by the request between the first server node and the first peripheral device via the second server node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the first peripheral device , F . a first bypass , executing on at least the first server node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first server node and the first peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit (parallel interface) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module (parallel interface) for writing the data item to the corresponding storage unit (parallel interface) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (parallel interface) of the second set contains valid data . 		EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (parallel interface) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (parallel interface) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit of the first set ;

wherein the storage unit writing module (parallel interface) is further configured to write the data item to the corresponding storage unit (parallel interface) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (parallel interface) of the third set contains valid data . 		EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (parallel interface) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (parallel interface) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (parallel interface) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (parallel interface) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (parallel interface) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0927942A2
CLAIM 1 A digital data processing system with access to information stored on a peripheral device , comprising A . first and second nodes coupled to one another over a first communications pathway , B . the second node being coupled to a peripheral device over a second communications pathway , C . the first node being coupled to the peripheral device over a third communications pathway , D . a file system , executing on the first and second nodes , being capable of responding to access requests generated by the first node , for (i) transferring data designated by the request between the first node and the peripheral device via the second node and via the first and second communications pathways , (ii) maintaining administrative information pertaining to storage of the data designated by the request on the peripheral device , E . a first bypass , executing on at least the first node , for interceding in response to at least a first selected access request applied thereby to the file system , by transferring data designated by that request between the first node and the peripheral device over the third communications pathway in accord with administrative information maintained by the file system pertaining to storage of that data on the peripheral storage device (data item) .

EP0927942A2
CLAIM 12 A digital data processing system according to claim 1 , wherein either : a) the first bypass selectively limit transfers between the first node and the peripheral device over the third communications pathway ;
and , optionally , wherein the first bypass selectively limits such transfers to facilitate access to the peripheral device by a node other than the first node and , optionally , wherein the bypass limits such transfers in accord with a predefined throttling limit ;
b) the first communications pathway comprises any of a wide area network interconnect , local area network interconnect , internet interconnect , or other network interconnect ;
or c) the third communications pathway comprises any of a fibre channel , a firewire bus , a serial storage architecture (SSA) bus , high-speed Ethernet bus , high performance parallel interface (storage unit writing module, storage unit update module, corresponding storage unit) (HPPI) bus , and other high-speed peripheral device bus .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US6108759A

Filed: 1997-09-17     Issued: 2000-08-22

Manipulation of partitions holding advanced file systems

(Original Assignee) Powerquest Corp     (Current Assignee) Veritas Technologies LLC

Niel Orcutt, Russell J. Marsh, Robert S. Raymond, Eric J. Ruff
US6618736B1
CLAIM 1 . A method for file system (file system structure) creation (file system structure) and archival comprising : providing a first set of storage units (one disk, two disk) and a second set of storage units , each storage unit (one disk, two disk) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 12 . The method of claim 1 , wherein the modifying step comprises updating a file system structure (file system creation, file systems, file system) which identifies bad sectors .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (one disk, two disk) are stored in a same storage device . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (one disk, two disk) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one disk, two disk) of the second set contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (one disk, two disk) of the second set contain valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk, two disk) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk, two disk) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (one disk, two disk) , each storage unit (one disk, two disk) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one disk, two disk) of the third set contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (one disk, two disk) of the third set contain valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk, two disk) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk, two disk) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk, two disk) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (one disk, two disk) of the second set for which an indication of valid data is stored in the first usage map . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units (one disk, two disk) with the third set of storage units . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (one disk, two disk) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (one disk, two disk) of the second set that is copied , storing an indication of valid data in the second usage map . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (file system structure) of a plurality of servers , the method comprising : providing a set of shared storage units (one disk, two disk) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (one disk, two disk) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 12 . The method of claim 1 , wherein the modifying step comprises updating a file system structure (file system creation, file systems, file system) which identifies bad sectors .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (file system structure) of each server comprises a combination of the set of shared storage units (one disk, two disk) and the first set of private storage units for the server . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 12 . The method of claim 1 , wherein the modifying step comprises updating a file system structure (file system creation, file systems, file system) which identifies bad sectors .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (one disk, two disk) and the first usage map of a first server . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (file system structure) for a second server using the stored template . 		US6108759A
CLAIM 12 . The method of claim 1 , wherein the modifying step comprises updating a file system structure (file system creation, file systems, file system) which identifies bad sectors .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (one disk, two disk) are stored in a same storage device . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (one disk, two disk) are stored a local storage device and the private storage units are stored in a remote storage device . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (one disk, two disk) contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (one disk, two disk) contain valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk, two disk) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk, two disk) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units (one disk, two disk) , each private storage unit (one disk, two disk) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (one disk, two disk) of the second set contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (one disk, two disk) of the second set contain valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk, two disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk, two disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk, two disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (one disk, two disk) of the first set for which an indication of valid data is stored in the first usage map . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (one disk, two disk) with the second set of private storage units . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (one disk, two disk) of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (one disk, two disk) of the first set that is copied , storing an indication of valid data in the second usage map . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (file system structure) within at least one storage device comprising a first set of storage units (one disk, two disk) and a second set of storage units , each storage unit (one disk, two disk) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 12 . The method of claim 1 , wherein the modifying step comprises updating a file system structure (file system creation, file systems, file system) which identifies bad sectors .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (one disk, two disk) are stored in a same storage device . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (one disk, two disk) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one disk, two disk) of the second set contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (one disk, two disk) of the second set contain valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk, two disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk, two disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (one disk, two disk) , each storage unit (one disk, two disk) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (one disk, two disk) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one disk, two disk) of the third set contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (one disk, two disk) of the third set contain valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk, two disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk, two disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk, two disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (one disk, two disk) of the second set for which an indication of valid data is stored in the first usage map . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units (one disk, two disk) with the third set of storage units . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (one disk, two disk) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (one disk, two disk) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (file system structure) within at least one storage device comprising a first set of storage units (one disk, two disk) and a second set of storage units , each storage unit (one disk, two disk) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6108759A
CLAIM 1 . A computer-implemented method for manipulating disk partitions , comprising the steps of : selecting a partition located on at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) attached to a disk drive , the partition having a left edge and a right edge and containing a plurality of sectors organized according to an advanced file system into user data and system data ;
and modifying the selected partition in place to produce a modified partition by resizing the clusters in the selected partition without destroying user data , the modified partition having a different cluster size than the selected partition and being organized according to the same advanced file system as the selected partition .

US6108759A
CLAIM 12 . The method of claim 1 , wherein the modifying step comprises updating a file system structure (file system creation, file systems, file system) which identifies bad sectors .

US6108759A
CLAIM 27 . The method of claim 14 , wherein the modifying step comprises replicating data between two disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) s .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5937159A

Filed: 1997-03-28     Issued: 1999-08-10

Secure computer system

(Original Assignee) Data General Corp     (Current Assignee) EMC Corp

William J. Meyers, Marc J. Fraioli, Jon F. Spencer
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (different one, first set) of storage units (system administrator) and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (system administrator) are stored in a same storage device . 		US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (different one, first set) of storage units (system administrator) is stored in a local storage device and the second set (second set) of storage units is stored in a remote storage device . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (second set) contains valid data . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (system administrator) of the second set (second set) contain valid data . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (different one, first set) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (different one, first set) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (system administrator) , each storage unit of the third set corresponding to one of the storage units of the first set (different one, first set) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (system administrator) of the third set contain valid data . 		US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (different one, first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (different one, first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (different one, first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (second set) of storage units (system administrator) with the third set of storage units . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (system administrator) of the second set (second set) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (authentication database) of a plurality of servers , the method comprising : providing a set of shared storage units (system administrator) ;

for each of the plurality of servers : providing a first set (different one, first set) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 23 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for creating initial authorization records in said authorization and authentication database (archiving file systems) when said computer system is installed .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units (system administrator) and the first set (different one, first set) of private storage units for the server . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (different one, first set) of private storage units (system administrator) and the first usage map of a first server . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (system administrator) are stored in a same storage device . 		US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (system administrator) are stored a local storage device and the private storage units are stored in a remote storage device . 		US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (system administrator) contain valid data . 		US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (second set) of private storage units (system administrator) , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (second set) contains valid data . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (system administrator) of the second set (second set) contain valid data . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (different one, first set) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (different one, first set) does not contain valid data , reading the data item from the shared storage unit . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (different one, first set) for which an indication of valid data is stored in the first usage map . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (different one, first set) of private storage units (system administrator) with the second set (second set) of private storage units . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (system administrator) of the first set (different one, first set) that contain valid data to those corresponding private storage units of the second set (second set) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (different one, first set) of storage units (system administrator) and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (system administrator) are stored in a same storage device . 		US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (different one, first set) of storage units (system administrator) is stored in a local storage device and the second set (second set) of storage units is stored in a remote storage device . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (second set) contains valid data . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (system administrator) of the second set (second set) contain valid data . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (different one, first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (different one, first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (system administrator) , each storage unit of the third set corresponding to one of the storage units of the first set (different one, first set) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (different one, first set) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (system administrator) of the third set contain valid data . 		US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (different one, first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (different one, first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (different one, first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (second set) of storage units (system administrator) with the third set of storage units . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (system administrator) of the second set (second set) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (different one, first set) of storage units (system administrator) and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5937159A
CLAIM 2 . A method for initiating a session in a trusted computer system having : (a) computer system hardware ;
(b) an operating system for controlling said hardware ;
(c) an authentication and authorization database stored in said hardware ;
(d) user software controlled by said operating system ;
(e) said user software including a plurality of software processes , each one of said processes functioning separately from the others ;
(f) said computer system hardware including means for isolating each one of said processes from the other to prevent any unauthorized operation of any one of said processes from affecting the operation of any other of said processes ;
(g) means for selecting one of said plurality of software processes as a Session Initiator (SI) ;
(h) means for selecting a different one (first set (first set) ) of said plurality of processes as the Credentials Daemon (CD) ;
said method comprising the steps of : (I) determining the parameters and constraints for said session ;
(II) sending an inquiry from the SI to the CD to ask the CD if said session is authorized ;
(III) the CD responding to said inquiry by determining if the session is authorized ;
and (IV) if the CD determines that said session is authorized , sending a first set of session credentials from the CD to the SI to initiate said session .

US5937159A
CLAIM 3 . The method according to claim 2 wherein the SI has a second set (second set) of credentials and where step (IV) additionally comprises merging said first set of credentials and said second set of credentials to form a merged set of credentials used by the new session .

US5937159A
CLAIM 24 . The computer system of claim 20 wherein at least one of said ADs additionally comprises means for allowing a system administrator (storage units) to add authorization records to said authorization and authentication database .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US6192389B1

Filed: 1997-03-28     Issued: 2001-02-20

Method and apparatus for transferring file descriptors in a multiprocess, multithreaded client/server system

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Donald F. Ault, Jeffrey D. Aman, Ernest S. Bender, Donna N. T. E. Dillenberger, David B. Emmes, Michael G. Spiegel
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage map of a first server (first server) . 		US6192389B1
CLAIM 1 . In a client/server system in which a first server (first server) process accepts an incoming work request from a client , said incoming work request specifying work to be performed by a second server process and having a descriptor associated therewith , said first and second server processes having first and second descriptor tables respectively associated therewith , a method of transferring said descriptor from said first server process to said second server process , comprising the steps of : in response to a request from said first server process , adding said work request to a queue of incoming work requests to enqueue said request and copying the descriptor associated with said enqueued work request from said first descriptor table to a temporary descriptor table associated with said enqueued work request ;
in response to a request from said second server process for more work , removing a work request from said queue to dequeue said request and copying the descriptor associated with said dequeued work request from the temporary descriptor table associated with said dequeued work request to said second descriptor table .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system for a second server (second server) using the stored template . 		US6192389B1
CLAIM 1 . In a client/server system in which a first server process accepts an incoming work request from a client , said incoming work request specifying work to be performed by a second server (second server) process and having a descriptor associated therewith , said first and second server processes having first and second descriptor tables respectively associated therewith , a method of transferring said descriptor from said first server process to said second server process , comprising the steps of : in response to a request from said first server process , adding said work request to a queue of incoming work requests to enqueue said request and copying the descriptor associated with said enqueued work request from said first descriptor table to a temporary descriptor table associated with said enqueued work request ;
in response to a request from said second server process for more work , removing a work request from said queue to dequeue said request and copying the descriptor associated with said dequeued work request from the temporary descriptor table associated with said dequeued work request to said second descriptor table .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6192389B1
CLAIM 10 . A program storage device (data item) readable by a machine , tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 1 .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		CN1162786A

Filed: 1997-01-30     Issued: 1997-10-22

用于多任务设施信息处理系统的资源管理方法和设备

(Original Assignee) 株式会社东芝     

沼尻裕, 酒井浩
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (理存储) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (理存储) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (理存储) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (理存储) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (理存储) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (理存储) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (理存储) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (理存储) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (理存储) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (理存储) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (理存储) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (理存储) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (理存储) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (理存储) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (理存储) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (理存储) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (理存储) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (理存储) to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (理存储) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (理存储) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (理存储) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。
US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code (计算机程序) for intercepting an attempt to write a data item (理存储) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		CN1162786A
CLAIM 4 . 一种用于计算机系统中的主存空间回收方法，其特征是包括步骤：确定用于选择其物理存储 (data item) 器页面欲被回收的进程的一组有序选择策略；确定一阈值；获取空闲主存(30)量；当空闲主存(30)量变成低于所述阈值时根据所述有序选择策略组在利用主存(30)的进程中选择一进程；和回收分配给该所选择进程的主存(30)。

CN1162786A
CLAIM 22 . 一种其中存储有计算机程序 (program code) 的存储媒体，所述计算机程序在由一处理器执行时能执行虚拟存储器计算机系统中的主存空间回收过程，其特征是所述计算机程序包括：周期地扫描一主存(30)的页面帧并回收最近未被访问的主存页面的出页面守护进程(20)；用于获取空闲主存(30)量的手段(10)；和用于按照空闲主存(30)量控制该出页面守护进程(20)扫描页面帧的速率的手段(10)。



US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0759592A2

Filed: 1996-08-01     Issued: 1997-02-26

System and method for file system lock and repair for a computer operating system

(Original Assignee) Sun Microsystems Inc     (Current Assignee) Sun Microsystems Inc

Steven T. Senator
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (file systems) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

EP0759592A2
CLAIM 6 The method of claim 1 further comprising the step of :    providing for allowing other threads corresponding to other operating system file systems (file systems) to continue while said failed file system is locked .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0759592A2
CLAIM 4 The method of claim 1 wherein said step of providing for locking further comprises the step of :    providing for marking blocks of data associated with said failed file system as inaccessable on an associated computer mass storage device (data item) .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5918018A

Filed: 1996-02-09     Issued: 1999-06-29

System and method for achieving network separation

(Original Assignee) Secure Computing LLC     (Current Assignee) McAfee LLC

Mark P. Gooderum, Trinh Q. Vu, Glenn Andreas
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (receiving information) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (receiving information) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (receiving information) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (data objects) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (data objects) contains valid data . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (data objects) contain valid data . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (data objects) contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (data objects) does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (data objects) does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage (receiving information) map . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units with the third set (data objects) of storage units . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set (data objects) that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (receiving information) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage (receiving information) map of a first server . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (receiving information) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (receiving information) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (receiving information) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (receiving information) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (receiving information) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (receiving information) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set for which an indication of valid data is stored in the first usage (receiving information) map . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (receiving information) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (receiving information) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (receiving information) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (data objects) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (data objects) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (data objects) contains valid data . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (data objects) contain valid data . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (data objects) contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (data objects) does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (data objects) does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage (receiving information) map . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units with the third set (data objects) of storage units . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set (data objects) that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5918018A
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (receiving information) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5918018A
CLAIM 9 . The method according to claim 2 , wherein the step of preventing a process from accessing burbs other than the burb to which the process is bound includes the step of limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0715250A2

Filed: 1995-11-29     Issued: 1996-06-05

Method of processing input/output request in computer system including a plurality of subsystems

(Original Assignee) NEC Corp     (Current Assignee) NEC Corp

Takahiro c/o NEC Corporation Okonogi
US6618736B1
CLAIM 1 . A method for file system (file system) creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit (one file) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 9 A method according to claim 8 , wherein said step (1-4) includes a step of : (1-4-1) storing said third information for each file system (file system) .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one file) of the second set contains valid data . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit (one file) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit (one file) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (one file) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one file) of the third set contains valid data . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit (one file) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit (one file) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit (one file) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (one file) of the second set for which an indication of valid data is stored in the first usage map . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (one file) of the second set that is copied , storing an indication of valid data in the second usage map . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (local input) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (one file) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

EP0715250A2
CLAIM 17 A method according to claim 16 , wherein said file information table indicates whether said at least one file , respectively , is to be processed by said function , said function comprising a local input (archiving file systems) /output function .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (file system) of each server comprises a combination of the set of shared storage units and the first set of private storage units for the server . 		EP0715250A2
CLAIM 9 A method according to claim 8 , wherein said step (1-4) includes a step of : (1-4-1) storing said third information for each file system (file system) .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (file system) for a second server (second access) using the stored template . 		EP0715250A2
CLAIM 7 A method according to claim 1 , wherein said first subsystem scores first access information indicative of access time of said device , and wherein said step (5) includes steps of : (5-1) storing second access (second server) information indicative of access time of said device in said second subsystem ;
and (5-2) updating said first access information according to said second access information .

EP0715250A2
CLAIM 9 A method according to claim 8 , wherein said step (1-4) includes a step of : (1-4-1) storing said third information for each file system (file system) .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (one file) contains valid data . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit (one file) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit (one file) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (one file) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (one file) of the second set contains valid data . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit (one file) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit (one file) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit (one file) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (one file) of the first set for which an indication of valid data is stored in the first usage map . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (one file) of the first set that is copied , storing an indication of valid data in the second usage map . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (file system) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (one file) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 9 A method according to claim 8 , wherein said step (1-4) includes a step of : (1-4-1) storing said third information for each file system (file system) .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one file) of the second set contains valid data . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit (one file) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit (one file) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (one file) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit (one file) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one file) of the third set contains valid data . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit (one file) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit (one file) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit (one file) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (one file) of the second set for which an indication of valid data is stored in the first usage map . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (one file) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (file system) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (one file) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0715250A2
CLAIM 3 A method according to claim 2 , wherein said device includes a storage device (data item) for storing a file , and wherein said step (3-1) includes a step of : (3-1-1) determining whether processing of said request accompanies at least one of a change in size of said file , expansion of said file , deletion of said file , and exclusive record control of said file .

EP0715250A2
CLAIM 9 A method according to claim 8 , wherein said step (1-4) includes a step of : (1-4-1) storing said third information for each file system (file system) .

EP0715250A2
CLAIM 16 A method according to claim 1 , wherein said device includes at least one file (storage unit, corresponding storage unit) stored therein , said method further comprising a step of holding a respective file information table for each file of said at least one file .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0709843A2

Filed: 1995-10-30     Issued: 1996-05-01

Method, apparatus and medium for data recording and processing

(Original Assignee) Sony Corp     (Current Assignee) Sony Corp

Tsutomu c/o Intellectual Property Div Yamamoto, Hiroyuki c/o Intellectual Property Div Fujita
US6618736B1
CLAIM 1 . A method for file system (data recording) creation (management data, link data) and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0709843A2
CLAIM 1 A randomly accessible recording medium , comprised of a data area in which recordal data is recorded in one or more variable length recording blocks by file and a management data (file system creation) area in which file entries and recording entries for each recording block of the files are recorded , the file entries including name data showing the names of the recordal data recorded in the files and identification data showing the record entries of the first recording blocks in which the recordal data are recorded , the record entries including head position data showing the heads of the recording blocks , link data (file system creation) showing the recording blocks in which continuations of the recordal data are recorded , and recording length data showing the recording lengths of the recording blocks .

EP0709843A2
CLAIM 3 A method of generating and recording recordal data on a randomly accessible recording medium and management data for managing that recordal data , comprised of the steps of : a) generating a file entry including name data showing the name of the recordal data , b) acquiring record entry nos . , c) writing the first record entry no . in the file entry as the head record entry no . , d) securing an empty recording area in the data recording (file systems, file system, storage unit reading module) area on the recording medium , e) writing the head position of the empty recording area in the record entry as head position data , f) recording the recordal data in the empty recording area , g) writing the size of the recorded recordal data in the record entry as the recording length data when the empty recording area becomes full and there is still recordal data remaining , h) acquiring the next record entry no . and writing the next record entry no . in the previous record entry as link data when there is still recordal data remaining , i) repeating steps d) to h) until there is no longer any recordal data to be recorded , and j) writing the size of the recordal data recorded in the recording area in the recording entry as the recording length data and writing link down showing that it is the end in the final record entry when there is no longer any recordal data to be recorded .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (data recording) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		EP0709843A2
CLAIM 3 A method of generating and recording recordal data on a randomly accessible recording medium and management data for managing that recordal data , comprised of the steps of : a) generating a file entry including name data showing the name of the recordal data , b) acquiring record entry nos . , c) writing the first record entry no . in the file entry as the head record entry no . , d) securing an empty recording area in the data recording (file systems, file system, storage unit reading module) area on the recording medium , e) writing the head position of the empty recording area in the record entry as head position data , f) recording the recordal data in the empty recording area , g) writing the size of the recorded recordal data in the record entry as the recording length data when the empty recording area becomes full and there is still recordal data remaining , h) acquiring the next record entry no . and writing the next record entry no . in the previous record entry as link data when there is still recordal data remaining , i) repeating steps d) to h) until there is no longer any recordal data to be recorded , and j) writing the size of the recordal data recorded in the recording area in the recording entry as the recording length data and writing link down showing that it is the end in the final record entry when there is no longer any recordal data to be recorded .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (data recording) of each server comprises a combination of the set of shared storage units and the first set of private storage units for the server . 		EP0709843A2
CLAIM 3 A method of generating and recording recordal data on a randomly accessible recording medium and management data for managing that recordal data , comprised of the steps of : a) generating a file entry including name data showing the name of the recordal data , b) acquiring record entry nos . , c) writing the first record entry no . in the file entry as the head record entry no . , d) securing an empty recording area in the data recording (file systems, file system, storage unit reading module) area on the recording medium , e) writing the head position of the empty recording area in the record entry as head position data , f) recording the recordal data in the empty recording area , g) writing the size of the recorded recordal data in the record entry as the recording length data when the empty recording area becomes full and there is still recordal data remaining , h) acquiring the next record entry no . and writing the next record entry no . in the previous record entry as link data when there is still recordal data remaining , i) repeating steps d) to h) until there is no longer any recordal data to be recorded , and j) writing the size of the recordal data recorded in the recording area in the recording entry as the recording length data and writing link down showing that it is the end in the final record entry when there is no longer any recordal data to be recorded .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (data recording) for a second server using the stored template . 		EP0709843A2
CLAIM 3 A method of generating and recording recordal data on a randomly accessible recording medium and management data for managing that recordal data , comprised of the steps of : a) generating a file entry including name data showing the name of the recordal data , b) acquiring record entry nos . , c) writing the first record entry no . in the file entry as the head record entry no . , d) securing an empty recording area in the data recording (file systems, file system, storage unit reading module) area on the recording medium , e) writing the head position of the empty recording area in the record entry as head position data , f) recording the recordal data in the empty recording area , g) writing the size of the recorded recordal data in the record entry as the recording length data when the empty recording area becomes full and there is still recordal data remaining , h) acquiring the next record entry no . and writing the next record entry no . in the previous record entry as link data when there is still recordal data remaining , i) repeating steps d) to h) until there is no longer any recordal data to be recorded , and j) writing the size of the recordal data recorded in the recording area in the recording entry as the recording length data and writing link down showing that it is the end in the final record entry when there is no longer any recordal data to be recorded .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (data recording) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0709843A2
CLAIM 3 A method of generating and recording recordal data on a randomly accessible recording medium and management data for managing that recordal data , comprised of the steps of : a) generating a file entry including name data showing the name of the recordal data , b) acquiring record entry nos . , c) writing the first record entry no . in the file entry as the head record entry no . , d) securing an empty recording area in the data recording (file systems, file system, storage unit reading module) area on the recording medium , e) writing the head position of the empty recording area in the record entry as head position data , f) recording the recordal data in the empty recording area , g) writing the size of the recorded recordal data in the record entry as the recording length data when the empty recording area becomes full and there is still recordal data remaining , h) acquiring the next record entry no . and writing the next record entry no . in the previous record entry as link data when there is still recordal data remaining , i) repeating steps d) to h) until there is no longer any recordal data to be recorded , and j) writing the size of the recordal data recorded in the recording area in the recording entry as the recording length data and writing link down showing that it is the end in the final record entry when there is no longer any recordal data to be recorded .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (data recording) configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0709843A2
CLAIM 3 A method of generating and recording recordal data on a randomly accessible recording medium and management data for managing that recordal data , comprised of the steps of : a) generating a file entry including name data showing the name of the recordal data , b) acquiring record entry nos . , c) writing the first record entry no . in the file entry as the head record entry no . , d) securing an empty recording area in the data recording (file systems, file system, storage unit reading module) area on the recording medium , e) writing the head position of the empty recording area in the record entry as head position data , f) recording the recordal data in the empty recording area , g) writing the size of the recorded recordal data in the record entry as the recording length data when the empty recording area becomes full and there is still recordal data remaining , h) acquiring the next record entry no . and writing the next record entry no . in the previous record entry as link data when there is still recordal data remaining , i) repeating steps d) to h) until there is no longer any recordal data to be recorded , and j) writing the size of the recordal data recorded in the recording area in the recording entry as the recording length data and writing link down showing that it is the end in the final record entry when there is no longer any recordal data to be recorded .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (data recording) configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0709843A2
CLAIM 3 A method of generating and recording recordal data on a randomly accessible recording medium and management data for managing that recordal data , comprised of the steps of : a) generating a file entry including name data showing the name of the recordal data , b) acquiring record entry nos . , c) writing the first record entry no . in the file entry as the head record entry no . , d) securing an empty recording area in the data recording (file systems, file system, storage unit reading module) area on the recording medium , e) writing the head position of the empty recording area in the record entry as head position data , f) recording the recordal data in the empty recording area , g) writing the size of the recorded recordal data in the record entry as the recording length data when the empty recording area becomes full and there is still recordal data remaining , h) acquiring the next record entry no . and writing the next record entry no . in the previous record entry as link data when there is still recordal data remaining , i) repeating steps d) to h) until there is no longer any recordal data to be recorded , and j) writing the size of the recordal data recorded in the recording area in the recording entry as the recording length data and writing link down showing that it is the end in the final record entry when there is no longer any recordal data to be recorded .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (data recording) configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		EP0709843A2
CLAIM 3 A method of generating and recording recordal data on a randomly accessible recording medium and management data for managing that recordal data , comprised of the steps of : a) generating a file entry including name data showing the name of the recordal data , b) acquiring record entry nos . , c) writing the first record entry no . in the file entry as the head record entry no . , d) securing an empty recording area in the data recording (file systems, file system, storage unit reading module) area on the recording medium , e) writing the head position of the empty recording area in the record entry as head position data , f) recording the recordal data in the empty recording area , g) writing the size of the recorded recordal data in the record entry as the recording length data when the empty recording area becomes full and there is still recordal data remaining , h) acquiring the next record entry no . and writing the next record entry no . in the previous record entry as link data when there is still recordal data remaining , i) repeating steps d) to h) until there is no longer any recordal data to be recorded , and j) writing the size of the recordal data recorded in the recording area in the recording entry as the recording length data and writing link down showing that it is the end in the final record entry when there is no longer any recordal data to be recorded .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (data recording) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0709843A2
CLAIM 3 A method of generating and recording recordal data on a randomly accessible recording medium and management data for managing that recordal data , comprised of the steps of : a) generating a file entry including name data showing the name of the recordal data , b) acquiring record entry nos . , c) writing the first record entry no . in the file entry as the head record entry no . , d) securing an empty recording area in the data recording (file systems, file system, storage unit reading module) area on the recording medium , e) writing the head position of the empty recording area in the record entry as head position data , f) recording the recordal data in the empty recording area , g) writing the size of the recorded recordal data in the record entry as the recording length data when the empty recording area becomes full and there is still recordal data remaining , h) acquiring the next record entry no . and writing the next record entry no . in the previous record entry as link data when there is still recordal data remaining , i) repeating steps d) to h) until there is no longer any recordal data to be recorded , and j) writing the size of the recordal data recorded in the recording area in the recording entry as the recording length data and writing link down showing that it is the end in the final record entry when there is no longer any recordal data to be recorded .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (data recording) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0709843A2
CLAIM 3 A method of generating and recording recordal data on a randomly accessible recording medium and management data for managing that recordal data , comprised of the steps of : a) generating a file entry including name data showing the name of the recordal data , b) acquiring record entry nos . , c) writing the first record entry no . in the file entry as the head record entry no . , d) securing an empty recording area in the data recording (file systems, file system, storage unit reading module) area on the recording medium , e) writing the head position of the empty recording area in the record entry as head position data , f) recording the recordal data in the empty recording area , g) writing the size of the recorded recordal data in the record entry as the recording length data when the empty recording area becomes full and there is still recordal data remaining , h) acquiring the next record entry no . and writing the next record entry no . in the previous record entry as link data when there is still recordal data remaining , i) repeating steps d) to h) until there is no longer any recordal data to be recorded , and j) writing the size of the recordal data recorded in the recording area in the recording entry as the recording length data and writing link down showing that it is the end in the final record entry when there is no longer any recordal data to be recorded .

US6618736B1
CLAIM 53 . An computer program product (first method) for creating and archiving a file system (data recording) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0709843A2
CLAIM 3 A method of generating and recording recordal data on a randomly accessible recording medium and management data for managing that recordal data , comprised of the steps of : a) generating a file entry including name data showing the name of the recordal data , b) acquiring record entry nos . , c) writing the first record entry no . in the file entry as the head record entry no . , d) securing an empty recording area in the data recording (file systems, file system, storage unit reading module) area on the recording medium , e) writing the head position of the empty recording area in the record entry as head position data , f) recording the recordal data in the empty recording area , g) writing the size of the recorded recordal data in the record entry as the recording length data when the empty recording area becomes full and there is still recordal data remaining , h) acquiring the next record entry no . and writing the next record entry no . in the previous record entry as link data when there is still recordal data remaining , i) repeating steps d) to h) until there is no longer any recordal data to be recorded , and j) writing the size of the recordal data recorded in the recording area in the recording entry as the recording length data and writing link down showing that it is the end in the final record entry when there is no longer any recordal data to be recorded .

EP0709843A2
CLAIM 8 A management apparatus for managing a randomly accessible recording medium comprised of at least one first recording area in which continuous data requiring continuous access is recorded in one or more variable length blocks by file and at least one second recording area in which random data not requiring continuous access is recorded in one or more fixed length blocks by file , the management data including data showing if the data recorded in a file is continuous data or random data , wherein the management apparatus manages the continuous data by a first method (computer program product) and manages the random data by a second method based on said management data .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5636371A

Filed: 1995-06-07     Issued: 1997-06-03

Virtual network mechanism to access well known port application programs running on a single host system

(Original Assignee) Bull HN Information Systems Inc     (Current Assignee) Bull HN Information Systems Inc

Kin C. Yu
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (first mapping, second mapping) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (first mapping, second mapping) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first mapping, second mapping) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first mapping, second mapping) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first mapping, second mapping) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first mapping, second mapping) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first mapping, second mapping) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first mapping, second mapping) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (first mapping, second mapping) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (first mapping, second mapping) of private storage units for the server . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (first mapping, second mapping) of private storage units and the first usage map of a first server (first mapping, second mapping) . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first mapping, second mapping) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first mapping, second mapping) does not contain valid data , reading the data item from the shared storage unit . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (first mapping, second mapping) for which an indication of valid data is stored in the first usage map . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (first mapping, second mapping) of private storage units with the second set of private storage units . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (first mapping, second mapping) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (first mapping, second mapping) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (first mapping, second mapping) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first mapping, second mapping) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first mapping, second mapping) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first mapping, second mapping) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (first mapping, second mapping) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first mapping, second mapping) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first mapping, second mapping) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first mapping, second mapping) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (first structure) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5636371A
CLAIM 6 . The method of claim 5 wherein the predetermined types of control data structures includes a first structure (storage unit update module) which defines the existence of the virtual network mechanism to the network software facility and a second structure which defines the virtual network mechanism .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (first mapping, second mapping) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5636371A
CLAIM 16 . The mechanism of claim 15 wherein each of said first and second mapping (first server, first set) components includes means for regenerating checksum for each inbound and outbound packet for enabling the network software facility of the lock host system to correctly process said each inbound and outbound packet by standard protocol procedures .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5706504A

Filed: 1995-06-07     Issued: 1998-01-06

Method and system for storing data objects using a small object data stream

(Original Assignee) Microsoft Corp     (Current Assignee) Microsoft Technology Licensing LLC

Robert G. Atkinson, Andrew L. Bliss, Philip J. Lafornara, Philip Ljubicich, Alexander G. Tilles, Antony S. Williams
US6618736B1
CLAIM 1 . A method for file system (file system) creation and archival comprising : providing a first set (defined size) of storage units and a second set of storage units , each storage unit (storing objects) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5706504A
CLAIM 8 . The method of claim 1 wherein the directory structure is arranged according to an MS-DOS file system (file system) architecture .

US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (defined size) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (storing objects) of the second set contains valid data . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (storing objects) of the first set (defined size) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (storing objects) of the first set (defined size) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (storing objects) of the third set corresponding to one of the storage units of the first set (defined size) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (storing objects) of the third set contains valid data . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (storing objects) of the first set (defined size) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (storing objects) of the first set (defined size) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (storing objects) of the first set (defined size) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (storing objects) of the second set for which an indication of valid data is stored in the first usage map . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (storing objects) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (defined size) of private storage units , each of the private storage units corresponding to a shared storage unit (storing objects) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (file system) of each server comprises a combination of the set of shared storage units and the first set (defined size) of private storage units for the server . 		US5706504A
CLAIM 8 . The method of claim 1 wherein the directory structure is arranged according to an MS-DOS file system (file system) architecture .

US5706504A
CLAIM 12 . A method in a computer system for storing objects of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (defined size) of private storage units and the first usage map of a first server . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (file system) for a second server using the stored template . 		US5706504A
CLAIM 8 . The method of claim 1 wherein the directory structure is arranged according to an MS-DOS file system (file system) architecture .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (storing objects) contains valid data . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (storing objects) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (storing objects) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (storing objects) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (storing objects) of the second set contains valid data . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (storing objects) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (storing objects) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (defined size) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (storing objects) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (defined size) does not contain valid data , reading the data item from the shared storage unit . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (storing objects) of the first set (defined size) for which an indication of valid data is stored in the first usage map . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (defined size) of private storage units with the second set of private storage units . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (defined size) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (storing objects) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (file system) within at least one storage device comprising a first set (defined size) of storage units and a second set of storage units , each storage unit (storing objects) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5706504A
CLAIM 8 . The method of claim 1 wherein the directory structure is arranged according to an MS-DOS file system (file system) architecture .

US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (defined size) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (storing objects) of the second set contains valid data . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (storing objects) of the first set (defined size) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (storing objects) of the first set (defined size) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (storing objects) of the third set corresponding to one of the storage units of the first set (defined size) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (storing objects) of the first set (defined size) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (storing objects) of the third set contains valid data . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (storing objects) of the first set (defined size) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (storing objects) of the first set (defined size) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (storing objects) of the first set (defined size) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (storing objects) of the second set for which an indication of valid data is stored in the first usage map . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (storing objects) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (file system) within at least one storage device comprising a first set (defined size) of storage units and a second set of storage units , each storage unit (storing objects) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5706504A
CLAIM 8 . The method of claim 1 wherein the directory structure is arranged according to an MS-DOS file system (file system) architecture .

US5706504A
CLAIM 12 . A method in a computer system for storing objects (storage unit) of varying sizes in a data storage area , the data storage area having a plurality of data storage sub-areas , the method comprising the steps of : allocating a data storage sub-area for storing multiple objects that are less than a predefined size (first set) ;
when an object is greater than or equal to the predefined size , allocating a data storage sub-area for the object ;
and storing the object in the allocated data storage sub-area for the object ;
and when an object is less than the predefined size , storing the object in a portion of the allocated data storage sub-area for storing objects that are less than the predefined size , such that a plurality of objects that are less than the predefined size are stored within a single storage sub-area .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5715441A

Filed: 1995-06-07     Issued: 1998-02-03

Method and system for storing and accessing data in a compound document using object linking

(Original Assignee) Microsoft Corp     (Current Assignee) Microsoft Technology Licensing LLC

Robert G. Atkinson, Andrew L. Bliss, Philip J. Lafornara, Philip Ljubicich, Alexander G. Tilles, Antony S. Williams
US6618736B1
CLAIM 1 . A method for file system (file system) creation and archival comprising : providing a first set (different application) of storage units and a second set of storage units , each storage unit (storing objects) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 4 . The method of claim 1 wherein the computer system has a file system (file system) , wherein the data storage area is a file , and the intermediate interface received from the application program includes functions that invoke the file system to effect the accessing of the data storage area .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (different application) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (storing objects) of the second set contains valid data . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (storing objects) of the first set (different application) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (storing objects) of the first set (different application) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (storing objects) of the third set corresponding to one of the storage units of the first set (different application) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (storing objects) of the third set contains valid data . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (storing objects) of the first set (different application) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (storing objects) of the first set (different application) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (storing objects) of the first set (different application) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (storing objects) of the second set for which an indication of valid data is stored in the first usage map . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (storing objects) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (different application) of private storage units , each of the private storage units corresponding to a shared storage unit (storing objects) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (file system) of each server comprises a combination of the set of shared storage units and the first set (different application) of private storage units for the server . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 4 . The method of claim 1 wherein the computer system has a file system (file system) , wherein the data storage area is a file , and the intermediate interface received from the application program includes functions that invoke the file system to effect the accessing of the data storage area .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (different application) of private storage units and the first usage map of a first server . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (file system) for a second server using the stored template . 		US5715441A
CLAIM 4 . The method of claim 1 wherein the computer system has a file system (file system) , wherein the data storage area is a file , and the intermediate interface received from the application program includes functions that invoke the file system to effect the accessing of the data storage area .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (storing objects) contains valid data . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (storing objects) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (storing objects) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (storing objects) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (storing objects) of the second set contains valid data . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (storing objects) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (storing objects) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (different application) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (storing objects) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (different application) does not contain valid data , reading the data item from the shared storage unit . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (storing objects) of the first set (different application) for which an indication of valid data is stored in the first usage map . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (different application) of private storage units with the second set of private storage units . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (different application) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (storing objects) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (file system) within at least one storage device comprising a first set (different application) of storage units and a second set of storage units , each storage unit (storing objects) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 4 . The method of claim 1 wherein the computer system has a file system (file system) , wherein the data storage area is a file , and the intermediate interface received from the application program includes functions that invoke the file system to effect the accessing of the data storage area .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (different application) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (storing objects) of the second set contains valid data . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (storing objects) of the first set (different application) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (storing objects) of the first set (different application) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (storing objects) of the third set corresponding to one of the storage units of the first set (different application) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (storing objects) of the first set (different application) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (storing objects) of the third set contains valid data . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (storing objects) of the first set (different application) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (storing objects) of the first set (different application) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (storing objects) of the first set (different application) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (storing objects) of the second set for which an indication of valid data is stored in the first usage map . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (storing objects) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (file system) within at least one storage device comprising a first set (different application) of storage units and a second set of storage units , each storage unit (storing objects) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5715441A
CLAIM 1 . A method in a computer system for storing data in a data storage area , the computer system having an application program that invokes a first application interface layer for accessing the data , the method comprising the steps of : under control of the application interface layer ;
receiving from the application program a reference to a second intermediate interface , the intermediate interface having a plurality of functions for accessing the data storage area , one of the functions for resizing the data storage area ;
receiving from the application program a request to access the data storage area ;
in response to receiving the request , invoking one or more functions of the intermediate interface received from the application program to effect : the accessing and resizing of the data storage area ;
and wherein the application interface layer can receive references to different implementations of the intermediate interface from different application (first set) programs .

US5715441A
CLAIM 4 . The method of claim 1 wherein the computer system has a file system (file system) , wherein the data storage area is a file , and the intermediate interface received from the application program includes functions that invoke the file system to effect the accessing of the data storage area .

US5715441A
CLAIM 5 . An object storage computer system for storing objects (storage unit) into a data storage area of the computer system comprising : a first application interface layer invocable by an application program , application interface layer providing a hierarchical organization for the storage of the objects , each object optionally having a subobject and optionally having object data , the application interface layer having a storage interface for enumerating ;
the subobjects of an object and for providing a stream interface for object data , the stream interface for accessing the object data ;
a second intermediate layer invocable by the application interface layer , the intermediate layer for providing a linear organization for the storage of data , the intermediate layer having an access interface for accessing the data of the storage ;
a third bottom layer invocable by the intermediate layer fear directly accessing the data storage area such that when an application program invokes the application interface layer , the application interface layer invokes the intermediate layer ;
and the intermediate layer invokes the bottom layer to directly access the data storage area and such that when an application program invokes the application interface layer , the application program specifies an implementation of the intermediate layer that is to be invoked by the application interface layer ;
and wherein different application programs can specify different implementations of the intermediate layer .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0683452A1

Filed: 1995-04-13     Issued: 1995-11-22

Partitioned log-structured file system and methods for operating same

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Thomas R. Engelmann, Kevin F. Smith, Aare Onton, Chia-Hon Chien
US6618736B1
CLAIM 1 . A method for file system (said first part, file system) creation and archival comprising : providing a first set of storage units (one disk) and a second set of storage units , each storage unit (one disk) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0683452A1
CLAIM 1 A data processing system comprising : a data processor ;
a disk data storage subsystem ;
and , a disk manager coupled to said disk data storage subsystem for controlling accesses to said disk data storage subsystem from said data processor , said disk manager managing said disk data storage subsystem as a log-structured file system (file system) having a first partition for storing segments comprised of active data units each of which has , when stored , an access activity value that exceeds a first predetermined threshold , and a second partition for storing segments comprised of inactive data units each of which has an access activity value , when stored , that is less than the first predetermined threshold .

EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

EP0683452A1
CLAIM 12 A method for operating a data processing system comprising a data processor , a disk data storage subsystem , and a disk manager , comprising the steps of :    partitioning the disk data storage system into multiple partitions including a first partition and a second partition ;
   managing at least said first part (file system) ition as a log-structured file system for storing segments comprised of active data units each having , when stored , an access activity value that exceeds a first predetermined threshold ;
and    storing , within the second partition , segments comprised of inactive data units each having an access activity value , when stored , that is less than the first predetermined threshold .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (one disk) are stored in a same storage device . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (one disk) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one disk) of the second set contains valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (one disk) of the second set contain valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (one disk) , each storage unit (one disk) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one disk) of the third set contains valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (one disk) of the third set contain valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (one disk) of the second set for which an indication of valid data is stored in the first usage map . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units (one disk) with the third set of storage units . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (one disk) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (one disk) of the second set that is copied , storing an indication of valid data in the second usage map . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (one disk) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (one disk) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (said first part, file system) of each server comprises a combination of the set of shared storage units (one disk) and the first set of private storage units for the server . 		EP0683452A1
CLAIM 1 A data processing system comprising : a data processor ;
a disk data storage subsystem ;
and , a disk manager coupled to said disk data storage subsystem for controlling accesses to said disk data storage subsystem from said data processor , said disk manager managing said disk data storage subsystem as a log-structured file system (file system) having a first partition for storing segments comprised of active data units each of which has , when stored , an access activity value that exceeds a first predetermined threshold , and a second partition for storing segments comprised of inactive data units each of which has an access activity value , when stored , that is less than the first predetermined threshold .

EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

EP0683452A1
CLAIM 12 A method for operating a data processing system comprising a data processor , a disk data storage subsystem , and a disk manager , comprising the steps of :    partitioning the disk data storage system into multiple partitions including a first partition and a second partition ;
   managing at least said first part (file system) ition as a log-structured file system for storing segments comprised of active data units each having , when stored , an access activity value that exceeds a first predetermined threshold ;
and    storing , within the second partition , segments comprised of inactive data units each having an access activity value , when stored , that is less than the first predetermined threshold .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (one disk) and the first usage map of a first server . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (said first part, file system) for a second server using the stored template . 		EP0683452A1
CLAIM 1 A data processing system comprising : a data processor ;
a disk data storage subsystem ;
and , a disk manager coupled to said disk data storage subsystem for controlling accesses to said disk data storage subsystem from said data processor , said disk manager managing said disk data storage subsystem as a log-structured file system (file system) having a first partition for storing segments comprised of active data units each of which has , when stored , an access activity value that exceeds a first predetermined threshold , and a second partition for storing segments comprised of inactive data units each of which has an access activity value , when stored , that is less than the first predetermined threshold .

EP0683452A1
CLAIM 12 A method for operating a data processing system comprising a data processor , a disk data storage subsystem , and a disk manager , comprising the steps of :    partitioning the disk data storage system into multiple partitions including a first partition and a second partition ;
   managing at least said first part (file system) ition as a log-structured file system for storing segments comprised of active data units each having , when stored , an access activity value that exceeds a first predetermined threshold ;
and    storing , within the second partition , segments comprised of inactive data units each having an access activity value , when stored , that is less than the first predetermined threshold .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (one disk) are stored in a same storage device . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (one disk) are stored a local storage device and the private storage units are stored in a remote storage device . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (one disk) contains valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (one disk) contain valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units (one disk) , each private storage unit (one disk) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (one disk) of the second set contains valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (one disk) of the second set contain valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (one disk) of the first set for which an indication of valid data is stored in the first usage map . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (one disk) with the second set of private storage units . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (one disk) of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (one disk) of the first set that is copied , storing an indication of valid data in the second usage map . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (said first part, file system) within at least one storage device comprising a first set of storage units (one disk) and a second set of storage units , each storage unit (one disk) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0683452A1
CLAIM 1 A data processing system comprising : a data processor ;
a disk data storage subsystem ;
and , a disk manager coupled to said disk data storage subsystem for controlling accesses to said disk data storage subsystem from said data processor , said disk manager managing said disk data storage subsystem as a log-structured file system (file system) having a first partition for storing segments comprised of active data units each of which has , when stored , an access activity value that exceeds a first predetermined threshold , and a second partition for storing segments comprised of inactive data units each of which has an access activity value , when stored , that is less than the first predetermined threshold .

EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

EP0683452A1
CLAIM 12 A method for operating a data processing system comprising a data processor , a disk data storage subsystem , and a disk manager , comprising the steps of :    partitioning the disk data storage system into multiple partitions including a first partition and a second partition ;
   managing at least said first part (file system) ition as a log-structured file system for storing segments comprised of active data units each having , when stored , an access activity value that exceeds a first predetermined threshold ;
and    storing , within the second partition , segments comprised of inactive data units each having an access activity value , when stored , that is less than the first predetermined threshold .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (one disk) are stored in a same storage device . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (one disk) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one disk) of the second set contains valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (one disk) of the second set contain valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (one disk) , each storage unit (one disk) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (one disk) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one disk) of the third set contains valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (one disk) of the third set contain valid data . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (one disk) of the second set for which an indication of valid data is stored in the first usage map . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units (one disk) with the third set of storage units . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (one disk) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (one disk) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (said first part, file system) within at least one storage device comprising a first set of storage units (one disk) and a second set of storage units , each storage unit (one disk) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0683452A1
CLAIM 1 A data processing system comprising : a data processor ;
a disk data storage subsystem ;
and , a disk manager coupled to said disk data storage subsystem for controlling accesses to said disk data storage subsystem from said data processor , said disk manager managing said disk data storage subsystem as a log-structured file system (file system) having a first partition for storing segments comprised of active data units each of which has , when stored , an access activity value that exceeds a first predetermined threshold , and a second partition for storing segments comprised of inactive data units each of which has an access activity value , when stored , that is less than the first predetermined threshold .

EP0683452A1
CLAIM 2 A system as claimed in claim 1 wherein the segments that are stored within the first partition are stored in physically adjacent tracks on at least one surface of at least one disk (storage units, storage unit, storage unit update module, corresponding storage unit, corresponding storage units) , wherein the physically adjacent tracks begin with an initial track , wherein the initial track is located at approximately the middle of all of the tracks on the surface , and wherein the other physically adjacent tracks are arrayed on both sides of the initial track .

EP0683452A1
CLAIM 12 A method for operating a data processing system comprising a data processor , a disk data storage subsystem , and a disk manager , comprising the steps of :    partitioning the disk data storage system into multiple partitions including a first partition and a second partition ;
   managing at least said first part (file system) ition as a log-structured file system for storing segments comprised of active data units each having , when stored , an access activity value that exceeds a first predetermined threshold ;
and    storing , within the second partition , segments comprised of inactive data units each having an access activity value , when stored , that is less than the first predetermined threshold .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0701716A1

Filed: 1994-06-02     Issued: 1996-03-20

A method for allocating files in a file system integrated with a raid disk sub-system

(Original Assignee) NETWORK APPLIANCE Corp     (Current Assignee) NETWORK APPLIANCE CORPORATION

David Hitz, James Lau, Michael Malcolm, Byron Rakitzis
US6618736B1
CLAIM 1 . A method for file system (file system) creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0701716A1
CLAIM 1 CLAIMS OF THE INVENTION 1 . A method for allocating files in a file system (file system) comprising : a) seled an inode having at least one dirty block from a list of inodes having dirty blocks ;
b) write allocate a tree of buffers referenced by said inode to a storage means in a RAID array ;
c) determine if all inodes in said list of inodes have been processed , when all of said inodes in said list of inodes have not been processed , continue repeating steps a-b ;
and , d) flush all unwritten stripes to said RAID array .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (file system) of each server comprises a combination of the set of shared storage units and the first set of private storage units for the server . 		EP0701716A1
CLAIM 1 CLAIMS OF THE INVENTION 1 . A method for allocating files in a file system (file system) comprising : a) seled an inode having at least one dirty block from a list of inodes having dirty blocks ;
b) write allocate a tree of buffers referenced by said inode to a storage means in a RAID array ;
c) determine if all inodes in said list of inodes have been processed , when all of said inodes in said list of inodes have not been processed , continue repeating steps a-b ;
and , d) flush all unwritten stripes to said RAID array .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (file system) for a second server using the stored template . 		EP0701716A1
CLAIM 1 CLAIMS OF THE INVENTION 1 . A method for allocating files in a file system (file system) comprising : a) seled an inode having at least one dirty block from a list of inodes having dirty blocks ;
b) write allocate a tree of buffers referenced by said inode to a storage means in a RAID array ;
c) determine if all inodes in said list of inodes have been processed , when all of said inodes in said list of inodes have not been processed , continue repeating steps a-b ;
and , d) flush all unwritten stripes to said RAID array .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (file system) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0701716A1
CLAIM 1 CLAIMS OF THE INVENTION 1 . A method for allocating files in a file system (file system) comprising : a) seled an inode having at least one dirty block from a list of inodes having dirty blocks ;
b) write allocate a tree of buffers referenced by said inode to a storage means in a RAID array ;
c) determine if all inodes in said list of inodes have been processed , when all of said inodes in said list of inodes have not been processed , continue repeating steps a-b ;
and , d) flush all unwritten stripes to said RAID array .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module (RAID array) configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage map . 		EP0701716A1
CLAIM 1 CLAIMS OF THE INVENTION 1 . A method for allocating files in a file system comprising : a) seled an inode having at least one dirty block from a list of inodes having dirty blocks ;
b) write allocate a tree of buffers referenced by said inode to a storage means in a RAID array (archival module) ;
c) determine if all inodes in said list of inodes have been processed , when all of said inodes in said list of inodes have not been processed , continue repeating steps a-b ;
and , d) flush all unwritten stripes to said RAID array .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (file system) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0701716A1
CLAIM 1 CLAIMS OF THE INVENTION 1 . A method for allocating files in a file system (file system) comprising : a) seled an inode having at least one dirty block from a list of inodes having dirty blocks ;
b) write allocate a tree of buffers referenced by said inode to a storage means in a RAID array ;
c) determine if all inodes in said list of inodes have been processed , when all of said inodes in said list of inodes have not been processed , continue repeating steps a-b ;
and , d) flush all unwritten stripes to said RAID array .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5442765A

Filed: 1991-12-19     Issued: 1995-08-15

Database system which adjusts the data storage order based on the processing speed of the storage media

(Original Assignee) NEC Corp     (Current Assignee) NEC Corp

Shoji Shiga
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (controlling means) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means) of the second set contains valid data . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (controlling means) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (controlling means) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (controlling means) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means) of the third set contains valid data . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (controlling means) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (controlling means) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means) of the second set contains valid data . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (controlling means) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (controlling means) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (controlling means) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means) of the third set contains valid data . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module (processing speeds) configured to merge the second set of storage units with the third set of storage units . 		US5442765A
CLAIM 1 . A method of retrieving storage units from and storing storage units to a database in a database system , the database containing a plurality of media , each of the media having a processing speed , the database system including a plurality of numerically designated system buffers , an input/output section , a control table , a medium storing area and a database control unit , the database system being accessed by a plurality of processing programs , the method comprising the steps of : retrieving , via the input/output section , storage units from the database in response to requests from the processing programs ;
storing each of the retrieved storage units in a separately numbered one of the system buffers ;
storing , in the medium storing area , for each retrieved storage unit , an indication of the processing speed of the medium from which the storage unit was retrieved ;
controlling , by updating the control table , the storage units to prevent access of the retrieved storage units by other processing programs ;
updating the storage units upon completion of a processing program ;
referring to the medium storing area to determine the processing speeds (merging module) of the media from which the storage units were retrieved ;
storing the updated storage units in the database in an order corresponding to the processing speeds of the media from which the storage units were retrieved , such that the storage units retrieved from media having higher processing speeds are stored before storage units retrieved from media having lower processing speeds ;
and releasing each of the storage units from control when the storage unit is written to the database .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module (processing speeds) is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5442765A
CLAIM 1 . A method of retrieving storage units from and storing storage units to a database in a database system , the database containing a plurality of media , each of the media having a processing speed , the database system including a plurality of numerically designated system buffers , an input/output section , a control table , a medium storing area and a database control unit , the database system being accessed by a plurality of processing programs , the method comprising the steps of : retrieving , via the input/output section , storage units from the database in response to requests from the processing programs ;
storing each of the retrieved storage units in a separately numbered one of the system buffers ;
storing , in the medium storing area , for each retrieved storage unit , an indication of the processing speed of the medium from which the storage unit was retrieved ;
controlling , by updating the control table , the storage units to prevent access of the retrieved storage units by other processing programs ;
updating the storage units upon completion of a processing program ;
referring to the medium storing area to determine the processing speeds (merging module) of the media from which the storage units were retrieved ;
storing the updated storage units in the database in an order corresponding to the processing speeds of the media from which the storage units were retrieved , such that the storage units retrieved from media having higher processing speeds are stored before storage units retrieved from media having lower processing speeds ;
and releasing each of the storage units from control when the storage unit is written to the database .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (controlling means) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5442765A
CLAIM 2 . A database system comprising : a database for storing a plurality of storage units assigned to different types of memory media having different processing speeds , the different types of memory media being accessible from a plurality of processing programs ;
a plurality of storing means , each storing means being adapted to read one of the storage units from the database and store said one of the storage units therein ;
exclusive controlling means (corresponding storage unit) for setting said one of the storage units being read to be under an exclusive control condition to prevent said one of the storage units from being accessed by other processing programs ;
medium speed storing means for storing the processing speed of the memory medium each time one of the storage units is read by one of said plurality of storing means ;
input/output means for reading storage units from the database to the storing means and writing storage units from the storing means to the database ;
and input/output control means for controlling the reading from and writing to the storing means ;
wherein the input/output means , in response to a write command from said input/output control means , refers to the medium speed storing means and writes the updated storage units to the database in order of the storage units assigned the highest speed memory medium , and wherein the input/output means updates the exclusive controlling means to release the applicable storage units from the exclusive control condition upon completion of writing to the database .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5212786A

Filed: 1991-04-01     Issued: 1993-05-18

File compaction process for electronic printing systems

(Original Assignee) Xerox Corp     (Current Assignee) Xerox Corp

Kitty Sathi
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (second sets, first set) of storage units (controlling means, one disk) and a second set of storage units , each storage unit (controlling means, one disk) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (controlling means, one disk) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US5212786A
CLAIM 7 . A process for compacting scattered contiguous and non-contiguous files in an electronic printing system having a system memory operatively coupled with N disks on which said files are stored , a processor for writing data , represented by electrical signals , from said system memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , wherein said files are moved from different areas of said disks to a predetermined area of said disks , some of said files comprising system files that are replicated and stored in duplicate on each of said disks to avoid loss in the event of disk failure , with other files comprising non-replicated files that are divided into relatively small file segments , with the number of said file segments being an even multiple of N with every N file segments divided between said disks at the same location , the locations of said files being stored in a first allocation table , comprising the steps of : a) building a list of said replicated and non-replicated files stored on said disks by volume ;
b) sorting said files by the disk addresses of said files ;
c) building a temporary volume allocation table in said system memory ;
d) using said temporary allocation table , allocating said contiguous files to a first set of locations in said predetermined area of said disks ;
e) using said temporary allocation table , allocating said non-contiguous files to a second set of locations in said predetermined area of said disks , performing step d) substantially prior to performing step e) ;
f) writing a copy of said temporary volume allocation table to one of said disks for updating said allocation table on said disk ;
g) moving said contiguous and non-contiguous files to the first and second sets (first set, second sets) of locations allocated in said temporary volume allocation table with said controlling means ;
and g) erasing said temporary allocation table from said system memory .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets (second sets, first set) of storage units (controlling means, one disk) are stored in a same storage device . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US5212786A
CLAIM 7 . A process for compacting scattered contiguous and non-contiguous files in an electronic printing system having a system memory operatively coupled with N disks on which said files are stored , a processor for writing data , represented by electrical signals , from said system memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , wherein said files are moved from different areas of said disks to a predetermined area of said disks , some of said files comprising system files that are replicated and stored in duplicate on each of said disks to avoid loss in the event of disk failure , with other files comprising non-replicated files that are divided into relatively small file segments , with the number of said file segments being an even multiple of N with every N file segments divided between said disks at the same location , the locations of said files being stored in a first allocation table , comprising the steps of : a) building a list of said replicated and non-replicated files stored on said disks by volume ;
b) sorting said files by the disk addresses of said files ;
c) building a temporary volume allocation table in said system memory ;
d) using said temporary allocation table , allocating said contiguous files to a first set of locations in said predetermined area of said disks ;
e) using said temporary allocation table , allocating said non-contiguous files to a second set of locations in said predetermined area of said disks , performing step d) substantially prior to performing step e) ;
f) writing a copy of said temporary volume allocation table to one of said disks for updating said allocation table on said disk ;
g) moving said contiguous and non-contiguous files to the first and second sets (first set, second sets) of locations allocated in said temporary volume allocation table with said controlling means ;
and g) erasing said temporary allocation table from said system memory .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (second sets, first set) of storage units (controlling means, one disk) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US5212786A
CLAIM 7 . A process for compacting scattered contiguous and non-contiguous files in an electronic printing system having a system memory operatively coupled with N disks on which said files are stored , a processor for writing data , represented by electrical signals , from said system memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , wherein said files are moved from different areas of said disks to a predetermined area of said disks , some of said files comprising system files that are replicated and stored in duplicate on each of said disks to avoid loss in the event of disk failure , with other files comprising non-replicated files that are divided into relatively small file segments , with the number of said file segments being an even multiple of N with every N file segments divided between said disks at the same location , the locations of said files being stored in a first allocation table , comprising the steps of : a) building a list of said replicated and non-replicated files stored on said disks by volume ;
b) sorting said files by the disk addresses of said files ;
c) building a temporary volume allocation table in said system memory ;
d) using said temporary allocation table , allocating said contiguous files to a first set of locations in said predetermined area of said disks ;
e) using said temporary allocation table , allocating said non-contiguous files to a second set of locations in said predetermined area of said disks , performing step d) substantially prior to performing step e) ;
f) writing a copy of said temporary volume allocation table to one of said disks for updating said allocation table on said disk ;
g) moving said contiguous and non-contiguous files to the first and second sets (first set, second sets) of locations allocated in said temporary volume allocation table with said controlling means ;
and g) erasing said temporary allocation table from said system memory .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means, one disk) (controlling means, one disk) of the second set contains valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (controlling means, one disk) of the second set contain valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (controlling means, one disk) of the first set (second sets, first set) ;

and in response to the first usage map indicating that the corresponding storage unit (controlling means, one disk) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US5212786A
CLAIM 7 . A process for compacting scattered contiguous and non-contiguous files in an electronic printing system having a system memory operatively coupled with N disks on which said files are stored , a processor for writing data , represented by electrical signals , from said system memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , wherein said files are moved from different areas of said disks to a predetermined area of said disks , some of said files comprising system files that are replicated and stored in duplicate on each of said disks to avoid loss in the event of disk failure , with other files comprising non-replicated files that are divided into relatively small file segments , with the number of said file segments being an even multiple of N with every N file segments divided between said disks at the same location , the locations of said files being stored in a first allocation table , comprising the steps of : a) building a list of said replicated and non-replicated files stored on said disks by volume ;
b) sorting said files by the disk addresses of said files ;
c) building a temporary volume allocation table in said system memory ;
d) using said temporary allocation table , allocating said contiguous files to a first set of locations in said predetermined area of said disks ;
e) using said temporary allocation table , allocating said non-contiguous files to a second set of locations in said predetermined area of said disks , performing step d) substantially prior to performing step e) ;
f) writing a copy of said temporary volume allocation table to one of said disks for updating said allocation table on said disk ;
g) moving said contiguous and non-contiguous files to the first and second sets (first set, second sets) of locations allocated in said temporary volume allocation table with said controlling means ;
and g) erasing said temporary allocation table from said system memory .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (controlling means, one disk) of the first set (second sets, first set) ;

and in response to the first usage map indicating that the corresponding storage unit (controlling means, one disk) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US5212786A
CLAIM 7 . A process for compacting scattered contiguous and non-contiguous files in an electronic printing system having a system memory operatively coupled with N disks on which said files are stored , a processor for writing data , represented by electrical signals , from said system memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , wherein said files are moved from different areas of said disks to a predetermined area of said disks , some of said files comprising system files that are replicated and stored in duplicate on each of said disks to avoid loss in the event of disk failure , with other files comprising non-replicated files that are divided into relatively small file segments , with the number of said file segments being an even multiple of N with every N file segments divided between said disks at the same location , the locations of said files being stored in a first allocation table , comprising the steps of : a) building a list of said replicated and non-replicated files stored on said disks by volume ;
b) sorting said files by the disk addresses of said files ;
c) building a temporary volume allocation table in said system memory ;
d) using said temporary allocation table , allocating said contiguous files to a first set of locations in said predetermined area of said disks ;
e) using said temporary allocation table , allocating said non-contiguous files to a second set of locations in said predetermined area of said disks , performing step d) substantially prior to performing step e) ;
f) writing a copy of said temporary volume allocation table to one of said disks for updating said allocation table on said disk ;
g) moving said contiguous and non-contiguous files to the first and second sets (first set, second sets) of locations allocated in said temporary volume allocation table with said controlling means ;
and g) erasing said temporary allocation table from said system memory .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (controlling means, one disk) , each storage unit (controlling means, one disk) of the third set corresponding to one of the storage units of the first set (second sets, first set) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (controlling means, one disk) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US5212786A
CLAIM 7 . A process for compacting scattered contiguous and non-contiguous files in an electronic printing system having a system memory operatively coupled with N disks on which said files are stored , a processor for writing data , represented by electrical signals , from said system memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , wherein said files are moved from different areas of said disks to a predetermined area of said disks , some of said files comprising system files that are replicated and stored in duplicate on each of said disks to avoid loss in the event of disk failure , with other files comprising non-replicated files that are divided into relatively small file segments , with the number of said file segments being an even multiple of N with every N file segments divided between said disks at the same location , the locations of said files being stored in a first allocation table , comprising the steps of : a) building a list of said replicated and non-replicated files stored on said disks by volume ;
b) sorting said files by the disk addresses of said files ;
c) building a temporary volume allocation table in said system memory ;
d) using said temporary allocation table , allocating said contiguous files to a first set of locations in said predetermined area of said disks ;
e) using said temporary allocation table , allocating said non-contiguous files to a second set of locations in said predetermined area of said disks , performing step d) substantially prior to performing step e) ;
f) writing a copy of said temporary volume allocation table to one of said disks for updating said allocation table on said disk ;
g) moving said contiguous and non-contiguous files to the first and second sets (first set, second sets) of locations allocated in said temporary volume allocation table with said controlling means ;
and g) erasing said temporary allocation table from said system memory .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means, one disk) (controlling means, one disk) of the third set contains valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (controlling means, one disk) of the third set contain valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (controlling means, one disk) of the first set (second sets, first set) ;

and in response to the second usage map indicating that the corresponding storage unit (controlling means, one disk) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US5212786A
CLAIM 7 . A process for compacting scattered contiguous and non-contiguous files in an electronic printing system having a system memory operatively coupled with N disks on which said files are stored , a processor for writing data , represented by electrical signals , from said system memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , wherein said files are moved from different areas of said disks to a predetermined area of said disks , some of said files comprising system files that are replicated and stored in duplicate on each of said disks to avoid loss in the event of disk failure , with other files comprising non-replicated files that are divided into relatively small file segments , with the number of said file segments being an even multiple of N with every N file segments divided between said disks at the same location , the locations of said files being stored in a first allocation table , comprising the steps of : a) building a list of said replicated and non-replicated files stored on said disks by volume ;
b) sorting said files by the disk addresses of said files ;
c) building a temporary volume allocation table in said system memory ;
d) using said temporary allocation table , allocating said contiguous files to a first set of locations in said predetermined area of said disks ;
e) using said temporary allocation table , allocating said non-contiguous files to a second set of locations in said predetermined area of said disks , performing step d) substantially prior to performing step e) ;
f) writing a copy of said temporary volume allocation table to one of said disks for updating said allocation table on said disk ;
g) moving said contiguous and non-contiguous files to the first and second sets (first set, second sets) of locations allocated in said temporary volume allocation table with said controlling means ;
and g) erasing said temporary allocation table from said system memory .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (controlling means, one disk) of the first set (second sets, first set) ;

and in response to the second usage map indicating that the corresponding storage unit (controlling means, one disk) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US5212786A
CLAIM 7 . A process for compacting scattered contiguous and non-contiguous files in an electronic printing system having a system memory operatively coupled with N disks on which said files are stored , a processor for writing data , represented by electrical signals , from said system memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , wherein said files are moved from different areas of said disks to a predetermined area of said disks , some of said files comprising system files that are replicated and stored in duplicate on each of said disks to avoid loss in the event of disk failure , with other files comprising non-replicated files that are divided into relatively small file segments , with the number of said file segments being an even multiple of N with every N file segments divided between said disks at the same location , the locations of said files being stored in a first allocation table , comprising the steps of : a) building a list of said replicated and non-replicated files stored on said disks by volume ;
b) sorting said files by the disk addresses of said files ;
c) building a temporary volume allocation table in said system memory ;
d) using said temporary allocation table , allocating said contiguous files to a first set of locations in said predetermined area of said disks ;
e) using said temporary allocation table , allocating said non-contiguous files to a second set of locations in said predetermined area of said disks , performing step d) substantially prior to performing step e) ;
f) writing a copy of said temporary volume allocation table to one of said disks for updating said allocation table on said disk ;
g) moving said contiguous and non-contiguous files to the first and second sets (first set, second sets) of locations allocated in said temporary volume allocation table with said controlling means ;
and g) erasing said temporary allocation table from said system memory .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (controlling means, one disk) of the first set (second sets, first set) ;

and in response to the second usage map indicating that the corresponding storage unit (controlling means, one disk) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US5212786A
CLAIM 7 . A process for compacting scattered contiguous and non-contiguous files in an electronic printing system having a system memory operatively coupled with N disks on which said files are stored , a processor for writing data , represented by electrical signals , from said system memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , wherein said files are moved from different areas of said disks to a predetermined area of said disks , some of said files comprising system files that are replicated and stored in duplicate on each of said disks to avoid loss in the event of disk failure , with other files comprising non-replicated files that are divided into relatively small file segments , with the number of said file segments being an even multiple of N with every N file segments divided between said disks at the same location , the locations of said files being stored in a first allocation table , comprising the steps of : a) building a list of said replicated and non-replicated files stored on said disks by volume ;
b) sorting said files by the disk addresses of said files ;
c) building a temporary volume allocation table in said system memory ;
d) using said temporary allocation table , allocating said contiguous files to a first set of locations in said predetermined area of said disks ;
e) using said temporary allocation table , allocating said non-contiguous files to a second set of locations in said predetermined area of said disks , performing step d) substantially prior to performing step e) ;
f) writing a copy of said temporary volume allocation table to one of said disks for updating said allocation table on said disk ;
g) moving said contiguous and non-contiguous files to the first and second sets (first set, second sets) of locations allocated in said temporary volume allocation table with said controlling means ;
and g) erasing said temporary allocation table from said system memory .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (controlling means, one disk) of the second set for which an indication of valid data is stored in the first usage map . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units (controlling means, one disk) with the third set of storage units . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (controlling means, one disk) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (controlling means, one disk) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (controlling means, one disk) ;

for each of the plurality of servers : providing a first set (second sets, first set) of private storage units , each of the private storage units corresponding to a shared storage unit (controlling means, one disk) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US5212786A
CLAIM 7 . A process for compacting scattered contiguous and non-contiguous files in an electronic printing system having a system memory operatively coupled with N disks on which said files are stored , a processor for writing data , represented by electrical signals , from said system memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , wherein said files are moved from different areas of said disks to a predetermined area of said disks , some of said files comprising system files that are replicated and stored in duplicate on each of said disks to avoid loss in the event of disk failure , with other files comprising non-replicated files that are divided into relatively small file segments , with the number of said file segments being an even multiple of N with every N file segments divided between said disks at the same location , the locations of said files being stored in a first allocation table , comprising the steps of : a) building a list of said replicated and non-replicated files stored on said disks by volume ;
b) sorting said files by the disk addresses of said files ;
c) building a temporary volume allocation table in said system memory ;
d) using said temporary allocation table , allocating said contiguous files to a first set of locations in said predetermined area of said disks ;
e) using said temporary allocation table , allocating said non-contiguous files to a second set of locations in said predetermined area of said disks , performing step d) substantially prior to performing step e) ;
f) writing a copy of said temporary volume allocation table to one of said disks for updating said allocation table on said disk ;
g) moving said contiguous and non-contiguous files to the first and second sets (first set, second sets) of locations allocated in said temporary volume allocation table with said controlling means ;
and g) erasing said temporary allocation table from said system memory .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units (controlling means, one disk) and the first set (second sets, first set) of private storage units for the server . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US5212786A
CLAIM 7 . A process for compacting scattered contiguous and non-contiguous files in an electronic printing system having a system memory operatively coupled with N disks on which said files are stored , a processor for writing data , represented by electrical signals , from said system memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , wherein said files are moved from different areas of said disks to a predetermined area of said disks , some of said files comprising system files that are replicated and stored in duplicate on each of said disks to avoid loss in the event of disk failure , with other files comprising non-replicated files that are divided into relatively small file segments , with the number of said file segments being an even multiple of N with every N file segments divided between said disks at the same location , the locations of said files being stored in a first allocation table , comprising the steps of : a) building a list of said replicated and non-replicated files stored on said disks by volume ;
b) sorting said files by the disk addresses of said files ;
c) building a temporary volume allocation table in said system memory ;
d) using said temporary allocation table , allocating said contiguous files to a first set of locations in said predetermined area of said disks ;
e) using said temporary allocation table , allocating said non-contiguous files to a second set of locations in said predetermined area of said disks , performing step d) substantially prior to performing step e) ;
f) writing a copy of said temporary volume allocation table to one of said disks for updating said allocation table on said disk ;
g) moving said contiguous and non-contiguous files to the first and second sets (first set, second sets) of locations allocated in said temporary volume allocation table with said controlling means ;
and g) erasing said temporary allocation table from said system memory .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (second sets, first set) of private storage units (controlling means, one disk) and the first usage map of a first server . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US5212786A
CLAIM 7 . A process for compacting scattered contiguous and non-contiguous files in an electronic printing system having a system memory operatively coupled with N disks on which said files are stored , a processor for writing data , represented by electrical signals , from said system memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , wherein said files are moved from different areas of said disks to a predetermined area of said disks , some of said files comprising system files that are replicated and stored in duplicate on each of said disks to avoid loss in the event of disk failure , with other files comprising non-replicated files that are divided into relatively small file segments , with the number of said file segments being an even multiple of N with every N file segments divided between said disks at the same location , the locations of said files being stored in a first allocation table , comprising the steps of : a) building a list of said replicated and non-replicated files stored on said disks by volume ;
b) sorting said files by the disk addresses of said files ;
c) building a temporary volume allocation table in said system memory ;
d) using said temporary allocation table , allocating said contiguous files to a first set of locations in said predetermined area of said disks ;
e) using said temporary allocation table , allocating said non-contiguous files to a second set of locations in said predetermined area of said disks , performing step d) substantially prior to performing step e) ;
f) writing a copy of said temporary volume allocation table to one of said disks for updating said allocation table on said disk ;
g) moving said contiguous and non-contiguous files to the first and second sets (first set, second sets) of locations allocated in said temporary volume allocation table with said controlling means ;
and g) erasing said temporary allocation table from said system memory .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (controlling means, one disk) are stored in a same storage device . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (controlling means, one disk) are stored a local storage device and the private storage units are stored in a remote storage device . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (controlling means, one disk) contains valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (controlling means, one disk) contain valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (controlling means, one disk) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (controlling means, one disk) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units (controlling means, one disk) , each private storage unit (controlling means, one disk) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (controlling means, one disk) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (controlling means, one disk) of the second set contains valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (controlling means, one disk) of the second set contain valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (controlling means, one disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (controlling means, one disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (second sets, first set) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (controlling means, one disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (second sets, first set) does not contain valid data , reading the data item from the shared storage unit . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (controlling means, one disk) of the first set (second sets, first set) for which an indication of valid data is stored in the first usage map . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (second sets, first set) of private storage units (controlling means, one disk) with the second set of private storage units . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (controlling means, one disk) of the first set (second sets, first set) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (controlling means, one disk) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (second sets, first set) of storage units (controlling means, one disk) and a second set of storage units , each storage unit (controlling means, one disk) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (controlling means, one disk) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets (second sets, first set) of storage units (controlling means, one disk) are stored in a same storage device . 		US5212786A
CLAIM 1 . In an electronic printing system having a system memory operatively coupled with N disks , a processor for writing data , represented by electrical signals , from said memory to said disks , and means for controlling movement of scattered replicated and non-replicated files between said disks , a process for compacting said scattered replicated and non-replicated files stored on said disks to locate said files in one area of said disks and free the remaining area of said disks for storing new files and file updates , said replicated and non-replicated files including contiguous files having a single run and non-contiguous files having plural runs , and a first file allocation table , identifying the current location of said files on said disks , comprising the steps of : a) building a list of said contiguous and noncontiguous files stored on said disks ;
b) sorting said files in said list in accordance with the location of said files on said disks ;
c) building a second file allocation table in said system memory ;
d) allocating a first set (first set, second sets) of locations to said contiguous files in said one area of said disks in said second allocation table ;
e) allocating a second set of locations to said non-contiguous files in said one area of said disks in said second allocation table , performing step d) substantially prior to performing step e) ;
f) writing a copy of said second allocation table to one of said disks with said processor to update said first allocation table ;
g) moving said contiguous and non-contiguous files to the respective first and second locations allocated for said files in said second allocation table with said controlling means (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) ;
and h) erasing said second allocation table from said system memory .

US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (second sets, first set) of storage units (controlling means, one disk) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means, one disk) (controlling means, one disk) of the second set contains valid data . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (controlling means, one disk) of the second set contain valid data . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (controlling means, one disk) of the first set (second sets, first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (controlling means, one disk) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (controlling means, one disk) of the first set (second sets, first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (controlling means, one disk) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (controlling means, one disk) , each storage unit (controlling means, one disk) of the third set corresponding to one of the storage units of the first set (second sets, first set) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (controlling means, one disk) of the first set (second sets, first set) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (controlling means, one disk) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means, one disk) (controlling means, one disk) of the third set contains valid data . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (controlling means, one disk) of the third set contain valid data . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (controlling means, one disk) of the first set (second sets, first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (controlling means, one disk) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (controlling means, one disk) of the first set (second sets, first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (controlling means, one disk) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (controlling means, one disk) of the first set (second sets, first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (controlling means, one disk) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (controlling means, one disk) of the second set for which an indication of valid data is stored in the first usage map . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units (controlling means, one disk) with the third set of storage units . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (controlling means, one disk) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (controlling means, one disk) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (second sets, first set) of storage units (controlling means, one disk) and a second set of storage units , each storage unit (controlling means, one disk) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (controlling means, one disk) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5212786A
CLAIM 6 . The process according to claim 1 including the steps of : a) dividing said non-replicated files into even sectors with the number of said sectors being an even multiple of said N disks ;
and b) allocating duplicate locations on each of said disks in said one disk (corresponding storage unit, storage units, storage unit, storage unit update module, corresponding storage units) area for every N sectors .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5088026A

Filed: 1990-02-09     Issued: 1992-02-11

Method for managing a data cache using virtual external storage addresses as arguments

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Gerald P. Bozman, George Eisenberger, Alexander S. Lett, James J. Myers, William H. Tetzlaff, Jay H. Unger
US6618736B1
CLAIM 1 . A method for file system (external storage) creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit (nonvolatile cache) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5088026A
CLAIM 1 . A CPU implemented method for managing a cache for external storage (file system) having a first and second page organized files including a data file versioning feature , said CPU including internal storage formed from RAM addressable pages and external storage formed from DASD addressable pages , comprising the steps of : (a) creating at least two named pages (FIG . 5 PAGE 0 , PAGE 1) in a predetermined file (FIG . 5 AV1) and assigning device independent locations in a logical external storage space (VF0 , VF1) ;
(b) writing the pages (PAGE 0 , PAGE 1) into a cache and indexing the cache location of said pages by the logical external storage space address (VF0 , VF1) ;
(c) responsive to an update of a page (FIG . 5 PAGE 1' ;
) not common to said first (AV1) and second (AV2) files , assigning another logical external storage space (VF2 for PAGE 1' ;
) and storing the updated pages in cache in said another storage space location ;
and (d) responsive to an update of a page common (PAGE 0) to the first (AV1) and second (AV2) files , updating the page in place in the cache (FIG . 6 VF0' ;
) , otherwise responsive to an update of a page not in common (PAGE 1" ;
) , writing the update in cache at yet another logical external storage space (FIG . 6 VF2" ;
) and retaining the original page at its former cache location (FIG . 6 VF2' ;
) .

US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US5088026A
CLAIM 4 . In a demand paging storage system of the type in which a CPU accesses each page according to its address in a linear , virtual address space from a RAM page organized cache , and further in which an accessed page not available in cache is staged from a location in an external backing store to said cache , each CPU page access to said cache including a virtual to real address translation , wherein a CPU implemented method for accessing pages in said cache without disturbing logical views of said pages and without having to assign additional backing store thereto , said logical views being expressed as a counterpart first and second page-organized file , comprises the steps of : (a) translating each CPU page access from the linear virtual page address to an address in a second line (file system creation) ar virtual address space representing cache locations , translating the address in the second linear virtual address space into a real address in the external backing store , and writing the page into the cache at its address in the second linear virtual address space from the backing store unless the page has already been written into the cache ;
and (b) responsive to each access from the CPU seeking to update a page stored in cache by writing the updated page in its second linear virtual address space cache location if the page is common to the first and second page organized files , otherwise , writing the updated page to another cache location having another second linear virtual address space address .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (nonvolatile cache) of the second set contains valid data . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (nonvolatile cache) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (nonvolatile cache) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (nonvolatile cache) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (nonvolatile cache) of the third set contains valid data . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (nonvolatile cache) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (nonvolatile cache) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (nonvolatile cache) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (nonvolatile cache) of the second set for which an indication of valid data is stored in the first usage map . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (nonvolatile cache) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (nonvolatile cache) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (external storage) of each server comprises a combination of the set of shared storage units and the first set of private storage units for the server . 		US5088026A
CLAIM 1 . A CPU implemented method for managing a cache for external storage (file system) having a first and second page organized files including a data file versioning feature , said CPU including internal storage formed from RAM addressable pages and external storage formed from DASD addressable pages , comprising the steps of : (a) creating at least two named pages (FIG . 5 PAGE 0 , PAGE 1) in a predetermined file (FIG . 5 AV1) and assigning device independent locations in a logical external storage space (VF0 , VF1) ;
(b) writing the pages (PAGE 0 , PAGE 1) into a cache and indexing the cache location of said pages by the logical external storage space address (VF0 , VF1) ;
(c) responsive to an update of a page (FIG . 5 PAGE 1' ;
) not common to said first (AV1) and second (AV2) files , assigning another logical external storage space (VF2 for PAGE 1' ;
) and storing the updated pages in cache in said another storage space location ;
and (d) responsive to an update of a page common (PAGE 0) to the first (AV1) and second (AV2) files , updating the page in place in the cache (FIG . 6 VF0' ;
) , otherwise responsive to an update of a page not in common (PAGE 1" ;
) , writing the update in cache at yet another logical external storage space (FIG . 6 VF2" ;
) and retaining the original page at its former cache location (FIG . 6 VF2' ;
) .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (external storage) for a second server using the stored template . 		US5088026A
CLAIM 1 . A CPU implemented method for managing a cache for external storage (file system) having a first and second page organized files including a data file versioning feature , said CPU including internal storage formed from RAM addressable pages and external storage formed from DASD addressable pages , comprising the steps of : (a) creating at least two named pages (FIG . 5 PAGE 0 , PAGE 1) in a predetermined file (FIG . 5 AV1) and assigning device independent locations in a logical external storage space (VF0 , VF1) ;
(b) writing the pages (PAGE 0 , PAGE 1) into a cache and indexing the cache location of said pages by the logical external storage space address (VF0 , VF1) ;
(c) responsive to an update of a page (FIG . 5 PAGE 1' ;
) not common to said first (AV1) and second (AV2) files , assigning another logical external storage space (VF2 for PAGE 1' ;
) and storing the updated pages in cache in said another storage space location ;
and (d) responsive to an update of a page common (PAGE 0) to the first (AV1) and second (AV2) files , updating the page in place in the cache (FIG . 6 VF0' ;
) , otherwise responsive to an update of a page not in common (PAGE 1" ;
) , writing the update in cache at yet another logical external storage space (FIG . 6 VF2" ;
) and retaining the original page at its former cache location (FIG . 6 VF2' ;
) .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (nonvolatile cache) contains valid data . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (nonvolatile cache) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (nonvolatile cache) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (nonvolatile cache) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (nonvolatile cache) of the second set contains valid data . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (nonvolatile cache) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (nonvolatile cache) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (nonvolatile cache) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (nonvolatile cache) of the first set for which an indication of valid data is stored in the first usage map . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (nonvolatile cache) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (external storage) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (nonvolatile cache) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5088026A
CLAIM 1 . A CPU implemented method for managing a cache for external storage (file system) having a first and second page organized files including a data file versioning feature , said CPU including internal storage formed from RAM addressable pages and external storage formed from DASD addressable pages , comprising the steps of : (a) creating at least two named pages (FIG . 5 PAGE 0 , PAGE 1) in a predetermined file (FIG . 5 AV1) and assigning device independent locations in a logical external storage space (VF0 , VF1) ;
(b) writing the pages (PAGE 0 , PAGE 1) into a cache and indexing the cache location of said pages by the logical external storage space address (VF0 , VF1) ;
(c) responsive to an update of a page (FIG . 5 PAGE 1' ;
) not common to said first (AV1) and second (AV2) files , assigning another logical external storage space (VF2 for PAGE 1' ;
) and storing the updated pages in cache in said another storage space location ;
and (d) responsive to an update of a page common (PAGE 0) to the first (AV1) and second (AV2) files , updating the page in place in the cache (FIG . 6 VF0' ;
) , otherwise responsive to an update of a page not in common (PAGE 1" ;
) , writing the update in cache at yet another logical external storage space (FIG . 6 VF2" ;
) and retaining the original page at its former cache location (FIG . 6 VF2' ;
) .

US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (nonvolatile cache) of the second set contains valid data . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (nonvolatile cache) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (nonvolatile cache) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (nonvolatile cache) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (nonvolatile cache) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (nonvolatile cache) of the third set contains valid data . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (nonvolatile cache) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (nonvolatile cache) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (nonvolatile cache) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (nonvolatile cache) of the second set for which an indication of valid data is stored in the first usage map . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (nonvolatile cache) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US6618736B1
CLAIM 53 . An computer program product (second page) for creating and archiving a file system (external storage) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (nonvolatile cache) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5088026A
CLAIM 2 . The method according to claim 1 , wherein said method includes the further steps as pertains to a nonvolatile cache (storage unit, storage unit reading module) of : (e) responsive to a full cache , allocating space on external storage (file system) , copying updated pages to that space , and forming a concordance between the logical external space location and the physical location in external storage .

US5088026A
CLAIM 4 . In a demand paging storage system of the type in which a CPU accesses each page according to its address in a linear , virtual address space from a RAM page organized cache , and further in which an accessed page not available in cache is staged from a location in an external backing store to said cache , each CPU page access to said cache including a virtual to real address translation , wherein a CPU implemented method for accessing pages in said cache without disturbing logical views of said pages and without having to assign additional backing store thereto , said logical views being expressed as a counterpart first and second page (computer program product) -organized file , comprises the steps of : (a) translating each CPU page access from the linear virtual page address to an address in a second linear virtual address space representing cache locations , translating the address in the second linear virtual address space into a real address in the external backing store , and writing the page into the cache at its address in the second linear virtual address space from the backing store unless the page has already been written into the cache ;
and (b) responsive to each access from the CPU seeking to update a page stored in cache by writing the updated page in its second linear virtual address space cache location if the page is common to the first and second page organized files , otherwise , writing the updated page to another cache location having another second linear virtual address space address .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5226160A

Filed: 1989-07-18     Issued: 1993-07-06

Method of and system for interactive video-audio-computer open architecture operation

(Original Assignee) Visage Inc     (Current Assignee) Visage Inc

James J. Waldron, Richard L. Ginga, Steven G. Corcoran
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (time t) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (device manager) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (device manager) of the second set contains valid data . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit (device manager) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit (device manager) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (device manager) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (device manager) of the third set contains valid data . 		US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (device manager) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (device manager) of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (device manager) of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage (time t) map . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (time t) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage (time t) map of a first server . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (device manager) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set for which an indication of valid data is stored in the first usage (time t) map . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (system software) for writing the data item to the corresponding storage unit (device manager) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 14 . A system as claimed in claim 10 and in which the system software (storage unit writing module, computer program product) comprises a two-dimensional matrix of executive file modules , each capable of communicating similarly with any other module , and with each row representing a layer of functionality , and with the highest row controlling the interface with other programs and the lowest row controlling the particular product or device .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (device manager) of the second set contains valid data . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (time t) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit (device manager) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit (device manager) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module (system software) is further configured to write the data item to the corresponding storage unit (device manager) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5226160A
CLAIM 14 . A system as claimed in claim 10 and in which the system software (storage unit writing module, computer program product) comprises a two-dimensional matrix of executive file modules , each capable of communicating similarly with any other module , and with each row representing a layer of functionality , and with the highest row controlling the interface with other programs and the lowest row controlling the particular product or device .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (device manager) of the third set contains valid data . 		US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (device manager) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (device manager) of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (device manager) of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage (time t) map . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (device manager) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .

US6618736B1
CLAIM 53 . An computer program product (system software) for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (device manager) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5226160A
CLAIM 1 . A method of interactive video-graphics-audio-computer open architecture operation for providing multi-media command and application functions through specific requested application programs that control the operation of requested multi-media hardware devices of various types including video overlay devices , video/graphics display devices , video disc player products , audio recording and playback devices and computer user input devices , that comprises , providing a modular interface buffering software layer between the application programs and the operating hardware required for performing the same , including providing multi-media command and control functions that manage the control and presentation of multi-media data and storage and display for said application programs independently of the type of the requested hardware device and its data format ;
optimizing the performance of such multi-media applications by interleaving data-intensive tasks , including loading graphics and audio files and dynamically loading at run-time only those descrete functions of multi-media command and control requested by the specific application programs under execution ;
and automatically selecting at run-time t (first usage) he hardware devices required to deliver the multi-media command and control functions requested , allowing the application program to be used with the hardware device requested without requiring any modification to the application software .

US5226160A
CLAIM 14 . A system as claimed in claim 10 and in which the system software (storage unit writing module, computer program product) comprises a two-dimensional matrix of executive file modules , each capable of communicating similarly with any other module , and with each row representing a layer of functionality , and with the highest row controlling the interface with other programs and the lowest row controlling the particular product or device .

US5226160A
CLAIM 17 . A system as claimed in claim 16 and in which the said logical layers of functionality in the successive matrix module rows include one or more of a kernel module , class manager modules , device manager (storage unit update module, corresponding storage unit) modules and device driver modules .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		JP2000348490A

Filed: 2000-04-18     Issued: 2000-12-15

メモリ装置

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

Hiroshi Takeda, 博 武田
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (アップ) of storage units and a second set (アップ) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (アップ) of storage units is stored in a local storage device and the second set (アップ) of storage units is stored in a remote storage device . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (アップ) contains valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (アップ) contain valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (アップ) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (アップ) contains valid data , reading the data item from the corresponding storage unit of the second set . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (アップ) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (アップ) does not contain valid data , reading the data item from the storage unit of the first set . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (アップ) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (アップ) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (アップ) contains valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (アップ) contain valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (アップ) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (アップ) contains valid data , reading the data item from the corresponding storage unit of the third set . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (アップ) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (アップ) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (アップ) contains valid data , reading the data item from the corresponding storage unit of the second set . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (アップ) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (アップ) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (アップ) does not contain valid data , reading the data item from the storage unit of the first set . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (アップ) for which an indication of valid data is stored in the first usage map . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (アップ) of storage units with the third set (アップ) of storage units . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (アップ) that contain valid data to those corresponding storage units of the third set (アップ) that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (アップ) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (アップ) of private storage units for the server . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (アップ) of private storage units and the first usage map of a first server . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (アップ) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (アップ) contains valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (アップ) contain valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (アップ) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (アップ) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (アップ) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (アップ) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (アップ) does not contain valid data , reading the data item from the shared storage unit . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (アップ) for which an indication of valid data is stored in the first usage map . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (アップ) of private storage units with the second set (アップ) of private storage units . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (アップ) that contain valid data to those corresponding private storage units of the second set (アップ) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (アップ) of storage units and a second set (アップ) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (アップ) of storage units is stored in a local storage device and the second set (アップ) of storage units is stored in a remote storage device . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (アップ) contains valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (アップ) contain valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (アップ) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (アップ) contains valid data , to read the data item from the corresponding storage unit of the second set . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (アップ) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (アップ) does not contain valid data , to read the data item from the storage unit of the first set . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (アップ) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (アップ) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (アップ) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (アップ) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (アップ) contains valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (アップ) contain valid data . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (アップ) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (アップ) contains valid data , to read the data item from the corresponding storage unit of the third set . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (アップ) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (アップ) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (アップ) contains valid data , to read the data item from the corresponding storage unit of the second set . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (アップ) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (アップ) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (アップ) does not contain valid data , to read the data item from the storage unit of the first set . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (アップ) for which an indication of valid data is stored in the first usage map . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (アップ) of storage units with the third set (アップ) of storage units . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (アップ) that contain valid data to those corresponding storage units of the third set (アップ) that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。
US6618736B1
CLAIM 53 . An computer program product (バーストモード) for creating and archiving a file system within at least one storage device comprising a first set (アップ) of storage units and a second set (アップ) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2000348490A
CLAIM 2 【請求項２】 上記メモリ装置は、バーストモード (computer program product) の 時、上記クロック信号の変化を計数することにより上記 データ入力／出力端子に入力又は出力される連続データ 数を検出し、上記連続データ数が所定の計数値に到達し た時、上記自励発振回路の発振動作を停止するカウンタ を更に含み、 上記バーストモードの時、１つのアクセス要求に応答し て、複数の連続データが上記クロック信号に同期して伝 送され、 上記アクセス要求は、上記制御信号と上記複数のアドレ ス信号とを含むものであることを特徴とする請求項１記 載のメモリ装置。

JP2000348490A
CLAIM 4 【請求項４】 上記読み出しデータは、上記タイミング 信号の変化エッジに対して所定のセットアップ (first set, second set, third set) 時間及び 所定のホールド時間を有するタイミングで出力されるも のであることを特徴とする請求項３記載の半導体装置。



US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP1039387A2

Filed: 2000-03-17     Issued: 2000-09-27

System and method for replicating data

(Original Assignee) Hitachi Ltd     (Current Assignee) Hitachi Ltd

Kouji c/o Hitachi Ltd Arai, Susumu c/o Hitachi Ltd Suzuki, Hironori c/o Hitachi Ltd Yasukawa
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units (volume identifier) and a second set of storage units , each storage unit (volume identifier) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (volume identifier) are stored in a same storage device . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (volume identifier) is stored in a local storage (volume identifier) device and the second set of storage units is stored in a remote storage device . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (volume identifier) of the second set contains valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (volume identifier) of the second set contain valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (volume identifier) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (volume identifier) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (volume identifier) , each storage unit (volume identifier) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (volume identifier) of the third set contains valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (volume identifier) of the third set contain valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (volume identifier) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (volume identifier) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (volume identifier) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (volume identifier) of the second set for which an indication of valid data is stored in the first usage map . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units (volume identifier) with the third set of storage units . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (volume identifier) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (volume identifier) of the second set that is copied , storing an indication of valid data in the second usage map . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (volume identifier) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (volume identifier) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units (volume identifier) and the first set of private storage units for the server . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (volume identifier) and the first usage map of a first server . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (volume identifier) are stored in a same storage device . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (volume identifier) are stored a local storage (volume identifier) device and the private storage units are stored in a remote storage device . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (volume identifier) contains valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (volume identifier) contain valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (volume identifier) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (volume identifier) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units (volume identifier) , each private storage unit (volume identifier) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (volume identifier) of the second set contains valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (volume identifier) of the second set contain valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (volume identifier) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (volume identifier) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (volume identifier) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (volume identifier) of the first set for which an indication of valid data is stored in the first usage map . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (volume identifier) with the second set of private storage units . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (volume identifier) of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (volume identifier) of the first set that is copied , storing an indication of valid data in the second usage map . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units (volume identifier) and a second set of storage units , each storage unit (volume identifier) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (volume identifier) are stored in a same storage device . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (volume identifier) is stored in a local storage (volume identifier) device and the second set of storage units is stored in a remote storage device . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (volume identifier) of the second set contains valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (volume identifier) of the second set contain valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (volume identifier) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (volume identifier) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (volume identifier) , each storage unit (volume identifier) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (volume identifier) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (volume identifier) of the third set contains valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (volume identifier) of the third set contain valid data . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (volume identifier) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (volume identifier) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (volume identifier) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (volume identifier) of the second set for which an indication of valid data is stored in the first usage map . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units (volume identifier) with the third set of storage units . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (volume identifier) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (volume identifier) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .

US6618736B1
CLAIM 53 . An computer program product (computer program product) for creating and archiving a file system within at least one storage device comprising a first set of storage units (volume identifier) and a second set of storage units , each storage unit (volume identifier) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP1039387A2
CLAIM 15 A computer program product (computer program product) for controlling the copying of information from a first logical volume to a second logical volume in a computer system , said computer program product comprising : code for specifying a relationship between said first logical volume and said second logical volume ;
code for creating a copy of data in said first logical volume into said second logical volume ;
said code for creating a copy further comprising : code for copying data from said first logical volume to a first location into a buffer memory ;
code for copying said data from said first location in said buffer memory to a second location in said buffer memory ;
code for copying said data from said second location in said buffer memory to said second logical volume ;
wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by a control unit substantially independently of a central processing unit ;
and a computer readable storage medium for holding the codes .

EP1039387A2
CLAIM 18 A control unit for controlling the copying of information , said control unit operable in a computing system comprising at least one of a plurality of storage devices , said control unit operable to control said storage devices , at least one of a plurality of processing units operable to access said control unit , said storage devices addressable as at least one of a plurality of logical volumes , including a first logical volume and a second logical volume , said control unit comprising a buffer memory operable to temporarily store data read from said storage devices within said control unit , said control unit operatively disposed to : copy data read from said first logical volume into a buffer memory located within said control unit ;
copy said data from said buffer memory to a different location within said buffer memory , changing a volume identifier (local storage, storage units, storage unit, local storage device, corresponding storage unit, corresponding storage units) associated with said data , and thereupon writing said data to said second logical volume ;
and wherein said copying said data from said first location in said buffer memory to a second location in said buffer memory is performed by said control unit substantially independently of a central processing unit .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		JP2001014257A

Filed: 1999-06-28     Issued: 2001-01-19

情報記録媒体交換装置及び情報記録媒体管理システム

(Original Assignee) Kubota Corp; 株式会社クボタ     

Toshiaki Mizukami, 利晃 水上
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (格納機構) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (ユニット) . 		JP2001014257A
CLAIM 4 【請求項４】 前記通信線(40)はＳＣＳＩバスであり、 前記機構群符号は論理ユニット (remote storage device) 番号であることを特徴と する請求項１乃至請求項３のいずれかに記載の情報記録 媒体交換装置。
US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (格納機構) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (格納機構) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (格納機構) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (格納機構) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (格納機構) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (格納機構) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (格納機構) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (ユニット) . 		JP2001014257A
CLAIM 4 【請求項４】 前記通信線(40)はＳＣＳＩバスであり、 前記機構群符号は論理ユニット (remote storage device) 番号であることを特徴と する請求項１乃至請求項３のいずれかに記載の情報記録 媒体交換装置。
US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (格納機構) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (格納機構) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (格納機構) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (格納機構) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (格納機構) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (格納機構) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (格納機構) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (ユニット) . 		JP2001014257A
CLAIM 4 【請求項４】 前記通信線(40)はＳＣＳＩバスであり、 前記機構群符号は論理ユニット (remote storage device) 番号であることを特徴と する請求項１乃至請求項３のいずれかに記載の情報記録 媒体交換装置。
US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (格納機構) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (格納機構) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (格納機構) to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (格納機構) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (格納機構) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (格納機構) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。
US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (格納機構) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2001014257A
CLAIM 1 【請求項１】 情報記録媒体(20)を挿入出する挿入出機 構(11)、挿入された情報記録媒体(20)を格納する複数の 格納機構 (data item) (12)、格納されている情報記録媒体(20)を装填 して記録されている情報を読み取る読取機構(13)、並び に挿入出機構(11)、格納機構(12)、及び読取機構(13)の 間で情報記録媒体(20)を搬送する搬送機構(14)を備え、 通信線(40)を介して制御装置(30)に接続される情報記録 媒体交換装置(10)において、 前記機構を含む複数の機構群の夫々に対応付けられる機 構群符号の割当を受け付ける手段(15a) と、 制御装置(30)から送信された機構群符号を含む命令信号 を受信する手段(15)と、 該命令信号に含まれる機構群符号を判別する手段(S101) と、 判別した機構群符号を割り当てられた機構群に含まれる 機構を、命令信号に基づいて制御する手段(S102)とを備 えることを特徴とする情報記録媒体交換装置。



US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		JPH11327991A

Filed: 1999-03-23     Issued: 1999-11-30

ホットスペアシステムおよびデ―タベ―ス管理システム

(Original Assignee) Lucent Technol Inc; ルーセント テクノロジーズ インコーポレイテッド     

Rajeev Rastogi, Abraham Silberschatz, シルバーシャッツ アブラハム, ラストジー ラジーフ
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device (少なくとも) and the second set of storage units is stored in a remote storage device . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the second set contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (パラメータ) of storage units , each storage unit (少なくとも) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the third set (パラメータ) contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (パラメータ) contain valid data . 		JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (パラメータ) contains valid data , reading the data item from the corresponding storage unit of the third set . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (パラメータ) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (パラメータ) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (少なくとも) of the second set for which an indication of valid data is stored in the first usage map . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units with the third set (パラメータ) of storage units . 		JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set (パラメータ) that do not contain valid data ;

and for each storage unit (少なくとも) of the second set that is copied , storing an indication of valid data in the second usage map . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (少なくとも) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device (少なくとも) and the private storage units are stored in a remote storage device . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (少なくとも) contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (少なくとも) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (少なくとも) of the second set contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (少なくとも) of the first set for which an indication of valid data is stored in the first usage map . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (少なくとも) of the first set that is copied , storing an indication of valid data in the second usage map . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device (少なくとも) and the second set of storage units is stored in a remote storage device . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the second set contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (パラメータ) of storage units , each storage unit (少なくとも) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (少なくとも) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (パラメータ) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the third set (パラメータ) contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (パラメータ) contain valid data . 		JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (パラメータ) contains valid data , to read the data item from the corresponding storage unit of the third set . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (パラメータ) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (パラメータ) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (少なくとも) of the second set for which an indication of valid data is stored in the first usage map . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。
US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units with the third set (パラメータ) of storage units . 		JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set (パラメータ) that do not contain valid data ;

and wherein the storage unit (少なくとも) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。

JPH11327991A
CLAIM 9 【請求項９】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ ア方法であって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）永続性データに関わるトランザクションのログレ コードをプライマリデータベースに保持するステップ と、 （Ｂ）ログレコードの少なくとも一部をセカンダリコン ピュータへと送り、セカンダリデータベースにログレコ ードのその少なくとも一部をコミットさせることをセカ ンダリコンピュータに可能にさせるステップと、 （Ｃ）プライマリコンピュータとセカンダリコンピュー タの状態をプライマリデータベースとセカンダリデータ ベースに関連づけられた第１パラメータ (third set) とするステップ とからなることを特徴とするホットスペア方法。
US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH11327991A
CLAIM 1 【請求項１】 プライマリコンピュータのホットスペア としてセカンダリコンピュータを動作させるホットスペ アシステムであって、 プライマリコンピュータは、プライマリデータベースを 有し、セカンダリデータベースを有するセカンダリコン ピュータと接続することができ、 （Ａ）プライマリデータベースと関連づけられ、プライ マリデータベース内の永続性データに関わるトランザク ションのログレコードを保持するトランザクションロガ ーと、 （Ｂ）プライマリデータベースと関連づけられ、２コン ピュータへログレコードの少なくとも (storage unit, local storage device) 一部を送り、セカ ンダリデータベースにログレコードのその少なくとも一 部をコミットさせることをセカンダリコンピュータに可 能にさせるトランザクションプロセッサとからなること を特徴とするホットスペアシステム。



US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		JP2000259583A

Filed: 1999-03-12     Issued: 2000-09-22

計算機システム

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

Yasuyuki Ajimatsu, Masatoshi Ichikawa, Hideki Kamimaki, Jun Matsumoto, Naoto Matsunami, Ikuya Yagisawa, Akira Yamamoto, Masayuki Yamamoto, 育哉 八木沢, 康行 味松, 山本　　彰, 山本　　政行, 正敏 市川, 直人 松並, 純 松本, 秀樹 神牧
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (アップ) of storage units and a second set (アップ) of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (アップ) of storage units is stored in a local storage device (少なくとも) and the second set (アップ) of storage units is stored in a remote storage device . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the second set (アップ) contains valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (アップ) contain valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。
US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (アップ) contains valid data , reading the data item from the corresponding storage unit of the second set . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (アップ) does not contain valid data , reading the data item from the storage unit of the first set . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (アップ) of storage units , each storage unit (少なくとも) of the third set corresponding to one of the storage units of the first set (アップ) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the third set (アップ) contains valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (アップ) contain valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。
US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (アップ) contains valid data , reading the data item from the corresponding storage unit of the third set . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (アップ) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (アップ) contains valid data , reading the data item from the corresponding storage unit of the second set . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (アップ) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (アップ) does not contain valid data , reading the data item from the storage unit of the first set . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (少なくとも) of the second set (アップ) for which an indication of valid data is stored in the first usage map . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (アップ) of storage units with the third set (アップ) of storage units . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。
US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (アップ) that contain valid data to those corresponding storage units of the third set (アップ) that do not contain valid data ;

and for each storage unit (少なくとも) of the second set that is copied , storing an indication of valid data in the second usage map . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (アップ) of private storage units , each of the private storage units corresponding to a shared storage unit (少なくとも) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (アップ) of private storage units for the server . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。
US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (アップ) of private storage units and the first usage map of a first server . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。
US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system for a second server (管理テーブル) using the stored template . 		JP2000259583A
CLAIM 5 【請求項５】前記管理コンソールは、各クライアント計 算機用の論理ボリュームを前記ストレージ内に作成する ための制御部を備え、 前記ストレージは、前記管理コンソールからの指令に従 って各クライアント計算機用の論理ボリュームを作成す る制御部と、各クライアント計算機から論理ボリューム へのアクセス制限情報を格納するための管理テーブル (second server) と、当該管理テーブルの情報に従ってクライアント計算 機からのアクセスを許可するかを判定するアクセス制御 部とを備えることを特徴とする請求項１に記載の計算機 システム。
US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device (少なくとも) and the private storage units are stored in a remote storage device . 		JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (少なくとも) contains valid data . 		JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (アップ) of private storage units , each private storage unit (少なくとも) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (少なくとも) of the second set (アップ) contains valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (アップ) contain valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。
US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (アップ) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (アップ) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (アップ) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (アップ) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (アップ) does not contain valid data , reading the data item from the shared storage unit . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (少なくとも) of the first set (アップ) for which an indication of valid data is stored in the first usage map . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (アップ) of private storage units with the second set (アップ) of private storage units . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。
US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (アップ) that contain valid data to those corresponding private storage units of the second set (アップ) that do not contain valid data ;

and for each private storage unit (少なくとも) of the first set that is copied , storing an indication of valid data in the second usage map . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (アップ) of storage units and a second set (アップ) of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (アップ) of storage units is stored in a local storage device (少なくとも) and the second set (アップ) of storage units is stored in a remote storage device . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the second set (アップ) contains valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (アップ) contain valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。
US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (アップ) contains valid data , to read the data item from the corresponding storage unit of the second set . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (アップ) does not contain valid data , to read the data item from the storage unit of the first set . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (アップ) of storage units , each storage unit (少なくとも) of the third set corresponding to one of the storage units of the first set (アップ) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (少なくとも) of the first set (アップ) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (アップ) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the third set (アップ) contains valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (アップ) contain valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。
US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (アップ) contains valid data , to read the data item from the corresponding storage unit of the third set . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (アップ) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (アップ) contains valid data , to read the data item from the corresponding storage unit of the second set . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (アップ) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (アップ) does not contain valid data , to read the data item from the storage unit of the first set . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (少なくとも) of the second set (アップ) for which an indication of valid data is stored in the first usage map . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (アップ) of storage units with the third set (アップ) of storage units . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。
US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (アップ) that contain valid data to those corresponding storage units of the third set (アップ) that do not contain valid data ;

and wherein the storage unit (少なくとも) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。
US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (アップ) of storage units and a second set (アップ) of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2000259583A
CLAIM 4 【請求項４】前記クライアント計算機はブートアップ (first set, second set, third set) 制 御回路を備え、前記ストレージはオペレーティングシス テム（OS)を格納し、前記ブートアップ制御回路は前記 ストレージに格納されたOSをブートすることを特徴とす る請求項１に記載の計算機システム。

JP2000259583A
CLAIM 6 【請求項６】前記管理コンソールは、少なくとも (storage unit, local storage device) ２台の クライアント計算機により共用される論理ボリュームを 作成するための制御部を備え、 前記ストレージは、管理コンソールからの指令に従って 前記共用される論理ボリュームを作成する制御部と、ク ライアント計算機から共用される論理ボリュームへのア クセス制限情報を格納するための管理テーブルと、当該 管理テーブルの情報に従ってクライアント計算機からの アクセスを許可するかを判定するアクセス制御部とを備 えることを特徴とする請求項１に記載の計算機システ ム。



US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		WO9941667A1

Filed: 1999-01-28     Issued: 1999-08-19

Memory module including a memory module controller

(Original Assignee) Intel Corporation     

Thomas J. Holman
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (first number) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (first number) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first number) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first number) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first number) ;

providing a second usage (data rate) map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage (data rate) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage (data rate) map comprises : initializing the second usage map to indicate that none of the storage units of the third set contain valid data . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first number) ;

and in response to the second usage (data rate) map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first number) ;

and in response to the second usage (data rate) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first number) ;

and in response to the second usage (data rate) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units (nonvolatile memory device) of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage (data rate) map . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 13 . The memory module of claim 1 , wherein the plurality of memory devices comprise nonvolatile memory device (corresponding storage units) s .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (first number) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (first number) of private storage units for the server . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (first number) of private storage units and the first usage map of a first server (second number) . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number (first server) of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage (data rate) map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage (data rate) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set contains valid data . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage (data rate) map comprises : initializing the second usage map to indicate that none of the private storage units of the second set contain valid data . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (data rate) map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (data rate) map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first number) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (data rate) map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first number) does not contain valid data , reading the data item from the shared storage unit . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (first number) for which an indication of valid data is stored in the first usage map . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (first number) of private storage units with the second set of private storage units . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (first number) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage (data rate) map . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (first number) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (first number) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first number) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first number) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first number) , the system further comprising a second usage (data rate) map for indicating which storage units of third set contain valid data . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (first number) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage (data rate) map that the corresponding storage unit of the third set contains valid data . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage (data rate) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage (data rate) map is initially reset to indicate that none of the storage units of the third set contain valid data . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first number) , the system further comprising : a storage unit reading module configured , in response to the second usage (data rate) map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first number) , the system further comprising : a storage unit reading module configured , in response to the second usage (data rate) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first number) , the system further comprising : a storage unit reading module configured , in response to the second usage (data rate) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module (write transaction) configured to merge the second set of storage units with the third set of storage units . 		WO9941667A1
CLAIM 15 . The memory module of claim 1 , wherein the memory transaction is a write transaction (merging module) .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module (write transaction) is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units (nonvolatile memory device) of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage (data rate) map . 		WO9941667A1
CLAIM 6 . The memory module of claim 1 , wherein the first memory bus operates at a first data rate (second usage, second usage map) and the second memory bus operates at a second data rate , wherein the first data rate is different than the second data rate .

WO9941667A1
CLAIM 13 . The memory module of claim 1 , wherein the plurality of memory devices comprise nonvolatile memory device (corresponding storage units) s .

WO9941667A1
CLAIM 15 . The memory module of claim 1 , wherein the memory transaction is a write transaction (merging module) .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (first number) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9941667A1
CLAIM 7 . The memory module of claim 1 , wherein the first memory bus has a first number (first set) of signals lines and the second memory bus has a second number of signal lines , wherein the first number of signal lines is different than the second number of signal lines .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		JP2000174505A

Filed: 1998-12-08     Issued: 2000-06-23

電子装置

(Original Assignee) Fujitsu Ltd; Hitachi Ltd; Matsushita Electronics Industry Corp; Mitsubishi Electric Corp; Nec Corp; Oki Electric Ind Co Ltd; Kanji Otsuka; Rohm Co Ltd; Sanyo Electric Co Ltd; Sharp Corp; Sony Corp; Toshiba Corp; Tamotsu Usami; シャープ株式会社; ソニー株式会社; ローム株式会社; 三洋電機株式会社; 三菱電機株式会社; 寛治 大塚; 保 宇佐美; 富士通株式会社; 日本電気株式会社; 松下電子工業株式会社; 株式会社日立製作所; 株式会社東芝; 沖電気工業株式会社     

Kanji Otsuka, Tamotsu Usami, 寛治 大塚, 保 宇佐美
US6618736B1
CLAIM 1 . A method for file system creation (受け取ること) and archival comprising : providing a first set of storage units and a second set (有する第１) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。

JP2000174505A
CLAIM 9 【請求項９】 請求項１記載の電子装置であって、前記 伝送線路のバス上に分岐してカレントスイッチ型のドラ イバ回路を有する第２の集積回路チップが接続され、前 記第１の集積回路チップがハイインピーダンスのレシー バ回路を有する構成において、前記第２の集積回路チッ プのドライバ回路から送った相補信号を前記第１の集積 回路チップのレシーバ回路で受け取ること (file system creation) を特徴とする 電子装置。
US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set (有する第１) of storage units is stored in a remote storage device . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (有する第１) contains valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (有する第１) contain valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (有する第１) contains valid data , reading the data item from the corresponding storage unit of the second set . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (有する第１) does not contain valid data , reading the data item from the storage unit of the first set . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage (有する第１) map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage (有する第１) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage (有する第１) map comprises : initializing the second usage map to indicate that none of the storage units of the third set contain valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage (有する第１) map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage (有する第１) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (有する第１) contains valid data , reading the data item from the corresponding storage unit of the second set . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage (有する第１) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (有する第１) does not contain valid data , reading the data item from the storage unit of the first set . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (有する第１) for which an indication of valid data is stored in the first usage map . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (有する第１) of storage units with the third set of storage units . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (有する第１) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage (有する第１) map . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (有する第１) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage (有する第１) map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage (有する第１) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (有する第１) contains valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage (有する第１) map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (有する第１) contain valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (有する第１) map indicating that the corresponding private storage unit of the second set (有する第１) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (有する第１) map indicating that the corresponding private storage unit of the second set (有する第１) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (有する第１) map indicating that the corresponding private storage unit of the second set (有する第１) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units with the second set (有する第１) of private storage units . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set (有する第１) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage (有する第１) map . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (有する第１) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set (有する第１) of storage units is stored in a remote storage device . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (有する第１) contains valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (有する第１) contain valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (有する第１) contains valid data , to read the data item from the corresponding storage unit of the second set . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (有する第１) does not contain valid data , to read the data item from the storage unit of the first set . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage (有する第１) map for indicating which storage units of third set contain valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage (有する第１) map that the corresponding storage unit of the third set contains valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage (有する第１) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage (有する第１) map is initially reset to indicate that none of the storage units of the third set contain valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (有する第１) map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (有する第１) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (有する第１) contains valid data , to read the data item from the corresponding storage unit of the second set . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (有する第１) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (有する第１) does not contain valid data , to read the data item from the storage unit of the first set . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (有する第１) for which an indication of valid data is stored in the first usage map . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (有する第１) of storage units with the third set of storage units . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (有する第１) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage (有する第１) map . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。
US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (有する第１) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JP2000174505A
CLAIM 1 【請求項１】 伝送線路と、この伝送線路に整合した終 端回路と、前記伝送線路および前記終端回路からなるバ ス配線系に相補信号を供給するドライバ回路とを有し、 前記伝送線路および前記終端回路を有する配線基板に、 前記ドライバ回路を有する第１ (second set, second usage) の集積回路チップが搭載 されてなる電子装置であって、前記伝送線路は、対向ペ ア線路構造で２５Ω以下の特性インピーダンスを有する 線路が並列等長配線され、２５Ω以下の純抵抗で終端さ れているバス構造であることを特徴とする電子装置。



US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		WO9912098A1

Filed: 1998-08-28     Issued: 1999-03-11

Data backup and recovery systems

(Original Assignee) Hewlett-Packard Company     

Stephen Gold, Jon Bathie, Peter King, Ian Peter Crighton
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (non-volatile memory, time t) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (non-volatile memory, time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (non-volatile memory, time t) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (non-volatile memory, time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (non-volatile memory, time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (non-volatile memory, time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (non-volatile memory, time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage (non-volatile memory, time t) map . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (secondary data) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (non-volatile memory, time t) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data (archiving file systems) storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage (non-volatile memory, time t) map of a first server . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (non-volatile memory, time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (non-volatile memory, time t) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (non-volatile memory, time t) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (non-volatile memory, time t) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (non-volatile memory, time t) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (non-volatile memory, time t) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set for which an indication of valid data is stored in the first usage (non-volatile memory, time t) map . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (non-volatile memory, time t) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module (non-volatile memory, time t) for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (non-volatile memory, time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (non-volatile memory, time t) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (non-volatile memory, time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (non-volatile memory, time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module (non-volatile memory, time t) is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (non-volatile memory, time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (non-volatile memory, time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage (non-volatile memory, time t) map . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (non-volatile memory, time t) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9912098A1
CLAIM 6 . Apparatus according to any one of the preceding claims , wherein the controller is programmed by instructions that are stored in non-volatile memory (first usage, first usage map, usage map updating module) of the controller , said instructions being read and processed as required by the controller .

WO9912098A1
CLAIM 15 . A method of backing up to a data backup and restore apparatus attached to a network data stored in one or more clients also attached to the network , the method comprising the data backup and restore apparatus storing in primary data storage a most recent version of all data received from the clients and , from time t (first usage, first usage map, usage map updating module) o time , in accordance with pre-determined criteria , storing in secondary data storage at least some of the data stored in the primary data storage .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0884732A2

Filed: 1998-06-10     Issued: 1998-12-16

Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system

(Original Assignee) Fujitsu Ltd     (Current Assignee) Fujitsu Ltd

Hisakatsu Araki, Kohtaroh Gotoh, Junji Ogawa, Hirotaka Tamura, Shigetoshi Wakayama
US6618736B1
CLAIM 1 . A method for file system creation (d line) and archival comprising : providing a first set (semiconductor chip, common value) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (time t) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (voltage conversion circuit, current signals) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

EP0884732A2
CLAIM 137 A phase interpolator as claimed in claim 123 , wherein said phase interpolator is configured so that the size of transistors to be switched and the quantization step size of a D/A converter are made variable to provide a desired line (file system creation) arity characteristic to a timing output versus a control signal .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (semiconductor chip, common value) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (input signals) . 		EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 70 A timing signal generating circuit as claimed in claim 57 , wherein said slave circuit includes a phase interpolator for accepting input signals (remote storage device) of different phases and for outputting a finer timing signal of an intermediate phase .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (voltage conversion circuit, current signals) of the second set contains valid data . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (semiconductor chip, common value) ;

and in response to the first usage (time t) map indicating that the corresponding storage unit (voltage conversion circuit, current signals) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (semiconductor chip, common value) ;

and in response to the first usage (time t) map indicating that the corresponding storage unit (voltage conversion circuit, current signals) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (value v) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (semiconductor chip, common value) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (voltage conversion circuit, current signals) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (voltage conversion circuit, current signals) of the third set (value v) contains valid data . 		EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (value v) contain valid data . 		EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (semiconductor chip, common value) ;

and in response to the second usage map indicating that the corresponding storage unit (voltage conversion circuit, current signals) of the third set (value v) contains valid data , reading the data item from the corresponding storage unit of the third set . 		EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (semiconductor chip, common value) ;

and in response to the second usage map indicating that the corresponding storage unit (voltage conversion circuit, current signals) of the third set (value v) does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (semiconductor chip, common value) ;

and in response to the second usage map indicating that the corresponding storage unit (voltage conversion circuit, current signals) of the third set (value v) does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage (time t) map . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units with the third set (value v) of storage units . 		EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units (latch circuits) of the third set (value v) that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		EP0884732A2
CLAIM 42 A signal transmission system as claimed in claim 36 , wherein said timing adjusting means includes a plurality of latch circuits (corresponding storage units) for latching said signals , and interleaving operations between two or more parts are performed using said plurality of latch circuits .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (semiconductor chip, common value) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (time t) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (semiconductor chip, common value) of private storage units for the server . 		EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (semiconductor chip, common value) of private storage units and the first usage (time t) map of a first server . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (input signals) . 		EP0884732A2
CLAIM 70 A timing signal generating circuit as claimed in claim 57 , wherein said slave circuit includes a phase interpolator for accepting input signals (remote storage device) of different phases and for outputting a finer timing signal of an intermediate phase .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (voltage conversion circuit, current signals) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set (semiconductor chip, common value) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set (semiconductor chip, common value) does not contain valid data , reading the data item from the shared storage unit . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (semiconductor chip, common value) for which an indication of valid data is stored in the first usage (time t) map . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (semiconductor chip, common value) of private storage units with the second set of private storage units . 		EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (semiconductor chip, common value) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (semiconductor chip, common value) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (voltage conversion circuit, current signals) for writing the data item to the corresponding storage unit (voltage conversion circuit, current signals) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (semiconductor chip, common value) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (input signals) . 		EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 70 A timing signal generating circuit as claimed in claim 57 , wherein said slave circuit includes a phase interpolator for accepting input signals (remote storage device) of different phases and for outputting a finer timing signal of an intermediate phase .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (voltage conversion circuit, current signals) of the second set contains valid data . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (time t) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (semiconductor chip, common value) , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit (voltage conversion circuit, current signals) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (semiconductor chip, common value) , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit (voltage conversion circuit, current signals) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (value v) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (semiconductor chip, common value) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (semiconductor chip, common value) ;

wherein the storage unit writing module (voltage conversion circuit, current signals) is further configured to write the data item to the corresponding storage unit (voltage conversion circuit, current signals) of the third set (value v) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (voltage conversion circuit, current signals) of the third set (value v) contains valid data . 		EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (value v) contain valid data . 		EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (semiconductor chip, common value) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (voltage conversion circuit, current signals) of the third set (value v) contains valid data , to read the data item from the corresponding storage unit of the third set . 		EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (semiconductor chip, common value) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (voltage conversion circuit, current signals) of the third set (value v) does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (semiconductor chip, common value) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (voltage conversion circuit, current signals) of the third set (value v) does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage (time t) map . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units with the third set (value v) of storage units . 		EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units (latch circuits) of the third set (value v) that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		EP0884732A2
CLAIM 42 A signal transmission system as claimed in claim 36 , wherein said timing adjusting means includes a plurality of latch circuits (corresponding storage units) for latching said signals , and interleaving operations between two or more parts are performed using said plurality of latch circuits .

EP0884732A2
CLAIM 123 A phase interpolator comprising : analog periodic waveform generating means for generating an analog periodic waveform whose value v (third set) aries in analog fashion , from a digital periodic signal whose amplitude represents a digital value ;
weighting control means for controlling the weighting of each of said analog periodic waveforms ;
summed waveform generating means for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generating means from digital periodic signals displaced along time axis ;
and analog/digital converting means for converting said summed waveform to a digital waveform .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (semiconductor chip, common value) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (voltage conversion circuit, current signals) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0884732A2
CLAIM 4 A semiconductor integrated circuit device as claimed in claim 1 , wherein said timing adjusting circuit includes : a first counter for counting said first clock ;
a second counter for counting said second clock ;
and a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time t (first usage) hat the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value .

EP0884732A2
CLAIM 14 A semiconductor integrated circuit device as claimed in claim 10 , wherein said command decoder includes a logic gate for enabling said common value (first set) indicated as the count value of said first counter for output to said timing buffer circuit only for a period during which said control command is issued .

EP0884732A2
CLAIM 72 A timing signal generating circuit as claimed in claim 70 , wherein said phase interpolator includes voltage-to-current converting means for converting a plurality of input voltage signals respectively to current signals (storage unit writing module, corresponding storage unit) , current-to-voltage converting means for converting said converted current signals back to voltage signals by varying voltage conversion factors , and comparing means for comparing a sum of said converted current signals with said reference signal .

EP0884732A2
CLAIM 74 A timing signal generating circuit as claimed in claim 73 , wherein a control current signal generating circuit for generating said control current signal is provided in said master circuit , and a current-to-voltage conversion circuit (storage unit writing module, corresponding storage unit) for converting said control current signal to a voltage signal is provided in said slave circuit .

EP0884732A2
CLAIM 79 A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit , said master circuit and said slave circuit being formed on the same semiconductor chip (first set) used for said semiconductor integrated circuit device , wherein : said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control ;
and said slave circuit generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and a control signal from said master circuit .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US6173377B1

Filed: 1998-04-17     Issued: 2001-01-09

Remote data mirroring

(Original Assignee) EMC Corp     (Current Assignee) EMC Corp

Moshe Yanai, Natan Vishlitzky, Bruno Alterescu, Daniel D. C Castel, Gadi G Shklarsky, Yuval Ofek
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (first set) of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set (first set) of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set (second set) of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (first set) of storage units is stored in a local storage device and the second set (second set) of storage units is stored in a remote storage device (background task) . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set (first set) of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set (second set) of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6173377B1
CLAIM 8 . The system as claimed in claim 4 , wherein the first data storage system includes a processor for performing a background task (remote storage device) of checking invalid track bits for data storage devices and if an invalid track bit is found to indicate an invalid track , a copy task is invoked to copy data from a known good storage device to the storage device having the invalid track .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (second set) contains valid data . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set (second set) of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (second set) contain valid data . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set (second set) of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first set) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set (first set) of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set (second set) of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first set) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set (first set) of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set (second set) of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first set) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set (first set) of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set (first set) of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set (first set) of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set (second set) of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set (first set) of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set (second set) of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set (second set) of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (second set) of storage units with the third set of storage units . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set (second set) of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (second set) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set (second set) of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (secondary storage device) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (first set) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set (first set) of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data (archiving file systems) storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6173377B1
CLAIM 11 . The system as claimed in claim 4 , wherein the first data storage system stores the data from the host computer to primary storage in the first data storage system when a secondary storage device (file systems) in the second data storage system is not available to store a remote copy of the data from the host computer , and as soon as the secondary storage device becomes available , then automatically , as a background operation , the first data storage system resynchronizes the secondary storage device with the primary storage in the first data storage system .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (first set) of private storage units for the server . 		US6173377B1
CLAIM 1 . A data storage system for providing remote data copying , said data storage system comprising : a first data storage subsystem including first data storage , and a second data storage subsystem including second data storage , the second data storage subsystem being at a location remote from the first data storage subsystem , and at least one data link between the first data storage subsystem and the second data storage subsystem for transmission of remote copy data from the first data storage subsystem to the second data storage subsystem , and for transmission of remote copy data from the second data storage subsystem to the first data storage subsystem ;
wherein the first data storage includes a first set (first set) of primary storage locations , and the second data storage includes a first set of secondary storage locations corresponding to the first set of primary storage locations ;
and the second data storage includes a second set of primary storage locations , and the first data storage includes a second set of secondary storage locations corresponding to the second set of primary storage locations ;
and wherein said first data storage subsystem maintains a first indicator providing an indication of whether a first specified data element stored in said first set of primary data storage locations is valid , a second indicator providing an indication of whether a valid secondary copy of said first specified data element is stored in said first set of secondary data storage locations , a third indicator providing an indication of whether a write is pending of said first specified data element to said first set of primary data storage locations , and at least a fourth indicator providing an indication of whether a write is pending of said first specified data element to said first set of secondary data storage locations , and wherein said second data storage subsystem maintains a fifth indicator providing an indication of whether a second specified data element stored in said second set of primary data storage locations is valid , a sixth indicator providing an indication of whether a valid secondary copy of said second specified data element is stored in said second set of secondary data storage locations , a seventh indicator providing an indication of whether a write is pending of said second specified data element to said second set of primary data storage locations , and at least an eighth indicator providing an indication of whether a write is pending of said second specified data element to said second set of secondary data storage locations .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (first set) of private storage units and the first usage map of a first server . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (background task) . 		US6173377B1
CLAIM 8 . The system as claimed in claim 4 , wherein the first data storage system includes a processor for performing a background task (remote storage device) of checking invalid track bits for data storage devices and if an invalid track bit is found to indicate an invalid track , a copy task is invoked to copy data from a known good storage device to the storage device having the invalid track .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (second set) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (second set) contains valid data . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (second set) contain valid data . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first set) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first set) does not contain valid data , reading the data item from the shared storage unit . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (first set) for which an indication of valid data is stored in the first usage map . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (first set) of private storage units with the second set (second set) of private storage units . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (first set) that contain valid data to those corresponding private storage units of the second set (second set) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (first set) of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (first set) of storage units is stored in a local storage device and the second set (second set) of storage units is stored in a remote storage device (background task) . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6173377B1
CLAIM 8 . The system as claimed in claim 4 , wherein the first data storage system includes a processor for performing a background task (remote storage device) of checking invalid track bits for data storage devices and if an invalid track bit is found to indicate an invalid track , a copy task is invoked to copy data from a known good storage device to the storage device having the invalid track .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (second set) contains valid data . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (second set) contain valid data . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first set) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (first set) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (second set) of storage units with the third set of storage units . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (second set) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (first set) of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6173377B1
CLAIM 3 . The system as claimed in claim 2 , wherein said first data storage subsystem maintains a first count of a number of data storage elements which are invalid in said first set (first set) of secondary data storage locations in said second data storage subsystem , and said first data storage subsystem transmits to said second data storage subsystem said first count of said number of data storage elements which are invalid in said first set of secondary data storage locations in said second data storage subsystem , and wherein said second data storage subsystem maintains a second count of a number of data storage elements which are invalid in said second set (second set) of secondary data storage locations in said first data storage subsystem , and said second data storage subsystem transmits to said first data storage subsystem said second count of said number of data storage elements which are invalid in said second set of secondary data storage locations in said first data storage subsystem .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US6026414A

Filed: 1998-03-05     Issued: 2000-02-15

System including a proxy client to backup files in a distributed computing environment

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Matthew Joseph Anglin
US6618736B1
CLAIM 1 . A method for file system (file system) creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6026414A
CLAIM 4 . The method of claim 2 , wherein the first and second computer machines include a distributed file system (file system) (DFS) client program and wherein the file server includes a DFS server program , wherein the DFS client program and DFS server program interface the first and second computer machines with the file server to allow access to files in the shared name space maintained by the file server .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (file system) of each server comprises a combination of the set of shared storage units and the first set of private storage units for the server . 		US6026414A
CLAIM 4 . The method of claim 2 , wherein the first and second computer machines include a distributed file system (file system) (DFS) client program and wherein the file server includes a DFS server program , wherein the DFS client program and DFS server program interface the first and second computer machines with the file server to allow access to files in the shared name space maintained by the file server .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (file system) for a second server using the stored template . 		US6026414A
CLAIM 4 . The method of claim 2 , wherein the first and second computer machines include a distributed file system (file system) (DFS) client program and wherein the file server includes a DFS server program , wherein the DFS client program and DFS server program interface the first and second computer machines with the file server to allow access to files in the shared name space maintained by the file server .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (file system) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6026414A
CLAIM 4 . The method of claim 2 , wherein the first and second computer machines include a distributed file system (file system) (DFS) client program and wherein the file server includes a DFS server program , wherein the DFS client program and DFS server program interface the first and second computer machines with the file server to allow access to files in the shared name space maintained by the file server .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6026414A
CLAIM 9 . A distributed computing system for backing up files in a shared name space , comprising : (a) a first backup client program , including means for initiating a backup request to backup a requested file ;
(b) a second backup client program ;
(c) a backup server program ;
(d) a storage device managed by the backup server program ;
(e) a file server , wherein the file server provides access (storage unit reading module, storage unit update module) to files included in a shared name space , wherein the first backup client program and the second backup client program have access to files maintained in the shared name space through the file server ;
(f) means for determining whether the requested file is included in the shared name space ;
(g) means for transmitting the backup request to the second backup client program upon determining that the requested file is included in the shared name space ;
(h) means for transmitting a message with the second backup client program to the file server to provide the requested file ;
(i) means , performed by the file server , for transmitting the requested file to the second backup client program ;
(j) means , performed by the second backup client program , for transmitting the requested file to the backup server program ;
and (k) means , performed by the backup server program , for storing the requested file in the storage device .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6026414A
CLAIM 9 . A distributed computing system for backing up files in a shared name space , comprising : (a) a first backup client program , including means for initiating a backup request to backup a requested file ;
(b) a second backup client program ;
(c) a backup server program ;
(d) a storage device managed by the backup server program ;
(e) a file server , wherein the file server provides access (storage unit reading module, storage unit update module) to files included in a shared name space , wherein the first backup client program and the second backup client program have access to files maintained in the shared name space through the file server ;
(f) means for determining whether the requested file is included in the shared name space ;
(g) means for transmitting the backup request to the second backup client program upon determining that the requested file is included in the shared name space ;
(h) means for transmitting a message with the second backup client program to the file server to provide the requested file ;
(i) means , performed by the file server , for transmitting the requested file to the second backup client program ;
(j) means , performed by the second backup client program , for transmitting the requested file to the backup server program ;
and (k) means , performed by the backup server program , for storing the requested file in the storage device .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6026414A
CLAIM 9 . A distributed computing system for backing up files in a shared name space , comprising : (a) a first backup client program , including means for initiating a backup request to backup a requested file ;
(b) a second backup client program ;
(c) a backup server program ;
(d) a storage device managed by the backup server program ;
(e) a file server , wherein the file server provides access (storage unit reading module, storage unit update module) to files included in a shared name space , wherein the first backup client program and the second backup client program have access to files maintained in the shared name space through the file server ;
(f) means for determining whether the requested file is included in the shared name space ;
(g) means for transmitting the backup request to the second backup client program upon determining that the requested file is included in the shared name space ;
(h) means for transmitting a message with the second backup client program to the file server to provide the requested file ;
(i) means , performed by the file server , for transmitting the requested file to the second backup client program ;
(j) means , performed by the second backup client program , for transmitting the requested file to the backup server program ;
and (k) means , performed by the backup server program , for storing the requested file in the storage device .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6026414A
CLAIM 9 . A distributed computing system for backing up files in a shared name space , comprising : (a) a first backup client program , including means for initiating a backup request to backup a requested file ;
(b) a second backup client program ;
(c) a backup server program ;
(d) a storage device managed by the backup server program ;
(e) a file server , wherein the file server provides access (storage unit reading module, storage unit update module) to files included in a shared name space , wherein the first backup client program and the second backup client program have access to files maintained in the shared name space through the file server ;
(f) means for determining whether the requested file is included in the shared name space ;
(g) means for transmitting the backup request to the second backup client program upon determining that the requested file is included in the shared name space ;
(h) means for transmitting a message with the second backup client program to the file server to provide the requested file ;
(i) means , performed by the file server , for transmitting the requested file to the second backup client program ;
(j) means , performed by the second backup client program , for transmitting the requested file to the backup server program ;
and (k) means , performed by the backup server program , for storing the requested file in the storage device .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6026414A
CLAIM 9 . A distributed computing system for backing up files in a shared name space , comprising : (a) a first backup client program , including means for initiating a backup request to backup a requested file ;
(b) a second backup client program ;
(c) a backup server program ;
(d) a storage device managed by the backup server program ;
(e) a file server , wherein the file server provides access (storage unit reading module, storage unit update module) to files included in a shared name space , wherein the first backup client program and the second backup client program have access to files maintained in the shared name space through the file server ;
(f) means for determining whether the requested file is included in the shared name space ;
(g) means for transmitting the backup request to the second backup client program upon determining that the requested file is included in the shared name space ;
(h) means for transmitting a message with the second backup client program to the file server to provide the requested file ;
(i) means , performed by the file server , for transmitting the requested file to the second backup client program ;
(j) means , performed by the second backup client program , for transmitting the requested file to the backup server program ;
and (k) means , performed by the backup server program , for storing the requested file in the storage device .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (provides access) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US6026414A
CLAIM 9 . A distributed computing system for backing up files in a shared name space , comprising : (a) a first backup client program , including means for initiating a backup request to backup a requested file ;
(b) a second backup client program ;
(c) a backup server program ;
(d) a storage device managed by the backup server program ;
(e) a file server , wherein the file server provides access (storage unit reading module, storage unit update module) to files included in a shared name space , wherein the first backup client program and the second backup client program have access to files maintained in the shared name space through the file server ;
(f) means for determining whether the requested file is included in the shared name space ;
(g) means for transmitting the backup request to the second backup client program upon determining that the requested file is included in the shared name space ;
(h) means for transmitting a message with the second backup client program to the file server to provide the requested file ;
(i) means , performed by the file server , for transmitting the requested file to the second backup client program ;
(j) means , performed by the second backup client program , for transmitting the requested file to the backup server program ;
and (k) means , performed by the backup server program , for storing the requested file in the storage device .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (file system) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6026414A
CLAIM 1 . A method for backing up files in a distributed computing system , comprising the steps of : maintaining , with a file server , files in a shared name space , wherein a first backup client program and a second backup client program are capable of accessing files in the shared name space via the file server ;
initiating a backup request with the first backup client program to backup a requested file ;
determining whether the requested file is maintained in the shared name space , transmitting the backup request from the first backup client program to the second backup client program upon determining that the requested file is maintained in the shared name space ;
transmitting a message with the second backup client program to the file server to provide the requested file ;
transmitting the requested file with the file server to the second backup client program ;
transmitting with the second backup client program the requested file to a backup server program ;
and storing with the backup server program the requested file in a storage device (data item) .

US6026414A
CLAIM 4 . The method of claim 2 , wherein the first and second computer machines include a distributed file system (file system) (DFS) client program and wherein the file server includes a DFS server program , wherein the DFS client program and DFS server program interface the first and second computer machines with the file server to allow access to files in the shared name space maintained by the file server .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0858031A1

Filed: 1998-01-15     Issued: 1998-08-12

Alternate boot record

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Viktors Berstis, George Lee Fulk
US6618736B1
CLAIM 1 . A method for file system (said first part) creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0858031A1
CLAIM 4 The method of claim 2 , further comprising : storing first extended boot data in said first part (file system) ition , said first extended boot data duplicating said primary boot data except for a flag indicating whether said first partition contains data for system initialization ;
and storing second extended boot data in said second partition , said second extended boot data duplicating said alternate boot data except for a flag indicating whether said second partition contains data for system initialization .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (native system, system error) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		EP0858031A1
CLAIM 5 A method in a data processing system for automatically reinitializing said data processing system , comprising : monitoring a periodic signal in said data processing system indicating normal operation ;
and responsive to a cessation of said periodic signal , automatically restarting said data processing system , wherein said data processing automatically recovers from system error (file systems) s without user intervention .

EP0858031A1
CLAIM 11 System initialization data in a data processing system , comprising : first system initialization data stored on computer readable media accessible by said data processing system ;
and second system initialization data stored on said computer readable media , said second system initialization data selectively accessible by said data processing system as an alternative to said first system initialization data , wherein said computer readable media contains alternative system (file systems) initialization data .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (said first part) of each server comprises a combination of the set of shared storage units and the first set of private storage units for the server . 		EP0858031A1
CLAIM 4 The method of claim 2 , further comprising : storing first extended boot data in said first part (file system) ition , said first extended boot data duplicating said primary boot data except for a flag indicating whether said first partition contains data for system initialization ;
and storing second extended boot data in said second partition , said second extended boot data duplicating said alternate boot data except for a flag indicating whether said second partition contains data for system initialization .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (said first part) for a second server using the stored template . 		EP0858031A1
CLAIM 4 The method of claim 2 , further comprising : storing first extended boot data in said first part (file system) ition , said first extended boot data duplicating said primary boot data except for a flag indicating whether said first partition contains data for system initialization ;
and storing second extended boot data in said second partition , said second extended boot data duplicating said alternate boot data except for a flag indicating whether said second partition contains data for system initialization .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (said first part) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0858031A1
CLAIM 4 The method of claim 2 , further comprising : storing first extended boot data in said first part (file system) ition , said first extended boot data duplicating said primary boot data except for a flag indicating whether said first partition contains data for system initialization ;
and storing second extended boot data in said second partition , said second extended boot data duplicating said alternate boot data except for a flag indicating whether said second partition contains data for system initialization .

US6618736B1
CLAIM 53 . An computer program product (computer program product) for creating and archiving a file system (said first part) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0858031A1
CLAIM 4 The method of claim 2 , further comprising : storing first extended boot data in said first part (file system) ition , said first extended boot data duplicating said primary boot data except for a flag indicating whether said first partition contains data for system initialization ;
and storing second extended boot data in said second partition , said second extended boot data duplicating said alternate boot data except for a flag indicating whether said second partition contains data for system initialization .

EP0858031A1
CLAIM 12 A computer program product (computer program product) for use with a data processing system , comprising : a computer usable medium ;
first instructions on said computer usable medium for storing primary boot data in said data processing system ;
second instructions on said computer usable medium for storing alternate boot data in said data processing system ;
third instructions on said computer usable medium for storing a first pointer in a controller associated with said data processing system , said first pointer pointing to said primary boot data ;
and fourth instructions on said computer usable medium for storing a second pointer in said controller , said second pointer pointing to said alternate boot data , wherein alternate boot data is accessible to said data processing system for utilization when said primary boot data may not be successfully utilized .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US6076148A

Filed: 1997-12-26     Issued: 2000-06-13

Mass storage subsystem and backup arrangement for digital data processing system which permits information to be backed up while host computer(s) continue(s) operating in connection with information stored on mass storage subsystem

(Original Assignee) EMC Corp     (Current Assignee) EMC Corp

Nadav Kedem
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (receiving information) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (receiving information) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (receiving information) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage (receiving information) map . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (receiving information) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage (receiving information) map of a first server . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (receiving information) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (receiving information) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (receiving information) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (receiving information) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (receiving information) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (receiving information) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set for which an indication of valid data is stored in the first usage (receiving information) map . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (receiving information) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (receiving information) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (receiving information) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (one track) configured , in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US6076148A
CLAIM 5 . A mass storage subsystem as defined in claim 1 in which said storage device comprises a disk storage device which stored information in a plurality of tracks , each storage block comprising one track (storage unit reading module) .

US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (one track) configured , in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US6076148A
CLAIM 5 . A mass storage subsystem as defined in claim 1 in which said storage device comprises a disk storage device which stored information in a plurality of tracks , each storage block comprising one track (storage unit reading module) .

US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (one track) configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US6076148A
CLAIM 5 . A mass storage subsystem as defined in claim 1 in which said storage device comprises a disk storage device which stored information in a plurality of tracks , each storage block comprising one track (storage unit reading module) .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (one track) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US6076148A
CLAIM 5 . A mass storage subsystem as defined in claim 1 in which said storage device comprises a disk storage device which stored information in a plurality of tracks , each storage block comprising one track (storage unit reading module) .

US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (one track) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US6076148A
CLAIM 5 . A mass storage subsystem as defined in claim 1 in which said storage device comprises a disk storage device which stored information in a plurality of tracks , each storage block comprising one track (storage unit reading module) .

US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage (receiving information) map . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (receiving information) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6076148A
CLAIM 6 . A mass storage subsystem as defined in claim 1 further comprising a backup subsystem for receiving information (first usage) from said backup interface and storing the received information on a backup storage medium .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0845906A2

Filed: 1997-10-31     Issued: 1998-06-03

Shared loop audio/video server system

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Ashok Kakkunje Adiga, Michael Norman Day, Kenneth Adam Kalinoski, Dale Arthur Legband, Wade David Shaw, Daniel Charles Wolfe, Donald Edwin Wood
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set (said server) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set (said server) of storage units is stored in a remote storage device . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (said server) contains valid data . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (said server) contain valid data . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (said server) contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (said server) does not contain valid data , reading the data item from the storage unit of the first set . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (said server) contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (said server) does not contain valid data , reading the data item from the storage unit of the first set . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (said server) for which an indication of valid data is stored in the first usage map . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (said server) of storage units with the third set of storage units . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (said server) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (said server) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (said server) contains valid data . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (said server) contain valid data . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (said server) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (said server) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (said server) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units with the second set (said server) of private storage units . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set (said server) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (said server) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set (said server) of storage units is stored in a remote storage device . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (said server) contains valid data . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (said server) contain valid data . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (said server) contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (said server) does not contain valid data , to read the data item from the storage unit of the first set . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (said server) contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (said server) does not contain valid data , to read the data item from the storage unit of the first set . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (said server) for which an indication of valid data is stored in the first usage map . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (said server) of storage units with the third set of storage units . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (said server) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .

US6618736B1
CLAIM 53 . An computer program product (accessed data) for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (said server) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0845906A2
CLAIM 1 A method for providing efficient multimedia datastreams in a multimedia system having a plurality of A/V servers , and a plurality of storage device (data item) s , said method comprising : interconnecting said storage devices in a shared communication loop ;
and interconnecting said A/V servers to said loop .

EP0845906A2
CLAIM 5 The method of Claim 3 wherein said system further includes archive server means controlled by said control server means , and archive storage system means interconnected to and controlled by said archive server means , and wherein said method further includes : accessing data on said archive storage system with said archive server means ;
and distributing said accessed data (computer program product) onto said shared communication loop with said archive server means .

EP0845906A2
CLAIM 17 A method for efficiently providing a datastream from a multimedia datastream system including at least one A/V device , a plurality of A/V servers , an archive server , and a shared loop storage subsystem , comprising the steps of : generating a request from said at least one A/V device to play a title ;
checking to determine if said title is available on said shared loop storage subsystem ;
requesting said archive server to load said title in response to said check indicating said title is not available on said shared loop storage subsystem ;
selecting one of said plurality of A/V servers to play said request ;
issuing said play request to said server (second set) ;
making an interconnection from said A/V server to said one A/V device ;
locating an prefetching blocks of data of said datastream stored on said shared loop storage subsystem by said A/V server ;
outputting an initial portion of said data comprising said datastream from said shared loop storage subsystem ;
checking data transfer integrity of said first portion of data ;
transferring said first portion of data from said A/V server to said at least one A/V device ;
prefetching successive next portions of data comprising said datastream from said shared loop storage subsystem by said A/V server ;
checking data transfer integrity of said next portion ;
repeating the immediately preceding two steps ;
checking for fetching of a last portion of said datastream ;
and disconnecting said connection after said check for said last portion of said datastream .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0859308A1

Filed: 1997-10-30     Issued: 1998-08-19

Library control device for logically dividing and controlling library device and method thereof

(Original Assignee) Fujitsu Ltd     (Current Assignee) Fujitsu Ltd

Yoshinori Terao
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (controlling means) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means) of the second set contains valid data . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (controlling means) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (controlling means) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (controlling means) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means) of the third set contains valid data . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (controlling means) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (controlling means) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means) of the second set contains valid data . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (controlling means) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (controlling means) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (controlling means) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means) of the third set contains valid data . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

US6618736B1
CLAIM 53 . An computer program product (readable recording medium) for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (controlling means) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0859308A1
CLAIM 1 A library control device (1) , comprising a memory means (11 , 33) for storing logical structure information representing a structure of a library device (22) divided into a plurality of logical units (LUN 0 , LUN 1 , LUN 2 , LUN 3) each suitable for independent control ;
and a controlling means (corresponding storage unit) (12 , 32) for controlling operation of said library device using said logical structure information .

EP0859308A1
CLAIM 25 A computer-readable recording medium (computer program product) (33) storing a program for directing a computer (1) to control operation of a library device (22) by dividing said library device into a plurality of logical units (LUN0 , LUN1 , LUN2 , LUN3) each suitable for independent control .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US6021415A

Filed: 1997-10-29     Issued: 2000-02-01

Storage management system with file aggregation and space reclamation within aggregated files

(Original Assignee) International Business Machines Corp     (Current Assignee) HGST Netherlands BV

David Maxwell Cannon, Howard Newton Martin
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set (including one) of storage units , each storage unit (processing apparatus, storage unit) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set (including one) of storage units is stored in a remote storage device . 		US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (processing apparatus, storage unit) of the second set (including one) contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (including one) contain valid data . 		US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit (processing apparatus, storage unit) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (including one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit (processing apparatus, storage unit) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (including one) does not contain valid data , reading the data item from the storage unit of the first set . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (processing apparatus, storage unit) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map (available storage space) for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map (available storage space) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (processing apparatus, storage unit) of the third set contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map (available storage space) comprises : initializing the second usage map to indicate that none of the storage units of the third set contain valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit (processing apparatus, storage unit) of the first set ;

and in response to the second usage map (available storage space) indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit (processing apparatus, storage unit) of the first set ;

and in response to the second usage map (available storage space) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (including one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit (processing apparatus, storage unit) of the first set ;

and in response to the second usage map (available storage space) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (including one) does not contain valid data , reading the data item from the storage unit of the first set . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (processing apparatus, storage unit) of the second set (including one) for which an indication of valid data is stored in the first usage map . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (including one) of storage units with the third set of storage units . 		US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (including one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (processing apparatus, storage unit) of the second set that is copied , storing an indication of valid data in the second usage map (available storage space) . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (processing apparatus, storage unit) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (processing apparatus, storage unit) contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit (processing apparatus, storage unit) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit (processing apparatus, storage unit) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (including one) of private storage units , each private storage unit (processing apparatus, storage unit) of the second set corresponding to one of the shared storage units ;

providing a second usage map (available storage space) for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map (available storage space) comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (processing apparatus, storage unit) of the second set (including one) contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map (available storage space) comprises : initializing the second usage map to indicate that none of the private storage units of the second set (including one) contain valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit (processing apparatus, storage unit) ;

and in response to the second usage map (available storage space) indicating that the corresponding private storage unit of the second set (including one) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit (processing apparatus, storage unit) ;

and in response to the second usage map (available storage space) indicating that the corresponding private storage unit of the second set (including one) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit (processing apparatus, storage unit) ;

and in response to the second usage map (available storage space) indicating that the corresponding private storage unit of the second set (including one) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (processing apparatus, storage unit) of the first set for which an indication of valid data is stored in the first usage map . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units with the second set (including one) of private storage units . 		US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set (including one) that do not contain valid data ;

and for each private storage unit (processing apparatus, storage unit) of the first set that is copied , storing an indication of valid data in the second usage map (available storage space) . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (including one) of storage units , each storage unit (processing apparatus, storage unit) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set (including one) of storage units is stored in a remote storage device . 		US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (processing apparatus, storage unit) of the second set (including one) contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (including one) contain valid data . 		US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit (processing apparatus, storage unit) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (including one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit (processing apparatus, storage unit) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (including one) does not contain valid data , to read the data item from the storage unit of the first set . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (processing apparatus, storage unit) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map (available storage space) for indicating which storage units of third set contain valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit (processing apparatus, storage unit) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map (available storage space) that the corresponding storage unit of the third set contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map (available storage space) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (processing apparatus, storage unit) of the third set contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map (available storage space) is initially reset to indicate that none of the storage units of the third set contain valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit (processing apparatus, storage unit) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map (available storage space) indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit (processing apparatus, storage unit) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map (available storage space) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (including one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit (processing apparatus, storage unit) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map (available storage space) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (including one) does not contain valid data , to read the data item from the storage unit of the first set . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (processing apparatus, storage unit) of the second set (including one) for which an indication of valid data is stored in the first usage map . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (including one) of storage units with the third set of storage units . 		US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (including one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (processing apparatus, storage unit) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map (available storage space) . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space (second usage map) in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .

US6618736B1
CLAIM 53 . An computer program product (digital processing) for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (including one) of storage units , each storage unit (processing apparatus, storage unit) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US6021415A
CLAIM 13 . The method of claim 8 , the managed file being stored in a first data storage unit (storage unit) , the evaluating of the managed file being performed in response to an absence of available storage space in the first data storage unit .

US6021415A
CLAIM 16 . A method of reclaiming a source storage area to a target storage area , said source storage area including one (second set) or more managed files , each managed file including one or more user files , said method comprising : evaluating the source storage area by determining whether data storage efficiency therein exceeds predetermined criteria ;
if the storage area fails the predetermined criteria , performing a reclamation process , said reclamation process comprising , for each managed file in the source storage area : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area to form a reconstructed managed file .

US6021415A
CLAIM 18 . The method of claim 16 , the source storage area comprising a data storage device (data item) .

US6021415A
CLAIM 33 . A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus (storage unit) to perform a method for reclaiming deleted-file storage space within a managed file originally created with a contiguous aggregation of user files , said deleted-file storage space arising from deletion of individual user files from the managed file , said managed file residing at a source storage area , said method comprising : determining whether the managed file contains any deleted-file storage space ;
in response to finding deleted-file storage space , performing a process of reconstructing the managed file comprising : identifying contiguous regions of non-deleted user files within the managed file ;
and copying each identified contiguous region to adjacent locations in a target storage area .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		WO9815897A1

Filed: 1997-10-06     Issued: 1998-04-16

Memory system and device

(Original Assignee) Hewlett-Packard Company     

Hans A. Wiggers
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (other memory, time t) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (other memory, time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (other memory, time t) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (other memory, time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (other memory, time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (other memory, time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (other memory, time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage (other memory, time t) map . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (other memory, time t) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage (other memory, time t) map of a first server (second number, shared data) . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 5 . An improvement according to claim 1 , 2 , 3 or 4 , said improvement further comprising : arrangement of at least two memory devices (105) on a single , shared data (first server) bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

WO9815897A1
CLAIM 22 . A memory system according to claims 19 or 20 wherein : both of the first and second memory devices are coupled to the controller (103) on a single , shared data bus (107) ;
said memory system (101) further comprises a third memory device which is coupled to the controller (103) on a second data bus , different from the shared data bus , the third memory also having a buffer (153) ;
the calibration mode of the controller (103) causes to poll the third memory device ;
the comparison device (118) additionally compares a timed response from the third memory device with time response for at least one of the first and second memory devices ;
the calibration mode of the controller (103) causes the controller to store a second number (first server) in the buffer (153) of the third memory , such that the third memory may be synchronized for simultaneous data delivery at the controller with one of the first and second memory devices .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (other memory, time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (other memory, time t) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (other memory, time t) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (other memory, time t) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (other memory, time t) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (other memory, time t) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set for which an indication of valid data is stored in the first usage (other memory, time t) map . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (other memory, time t) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module (other memory, time t) for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (other memory, time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (other memory, time t) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (other memory, time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (other memory, time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module (other memory, time t) is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (other memory, time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (other memory, time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage (other memory, time t) map . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (other memory, time t) map for indicating which storage units of the second set contain valid data ;

program code (data word) for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9815897A1
CLAIM 4 . An improvement according to claim 3 , further comprising : a delay adjustment mechanism within each memory device , the delay adjustment mechanism receiving a command from the command bus (111) and data from the data bus (107) , and calculating a deviation in time t (first usage, first usage map, usage map updating module) o the number for the corresponding memory device (105) , the number correcting for difference in travel time between the command bus (111) and the data bus (107) .

WO9815897A1
CLAIM 11 . A method according to claims 7 , 8 , 9 , or 10 , wherein each memory device (105) further includes a predetermined data word (program code) stored internally , said method further comprising : for each memory device (105) , in response to the signal , coupling the predetermined data word to at least one associated data bus (107) .

WO9815897A1
CLAIM 14 . A memory device (105) for use in a memory system (101) having a memory controller (103) and a system bus , wherein the memory controller (103) polls each of several memory elements (105) to determine an associated command response time and determines a desired response time , comprising : a memory space (141) wherein data is stored ;
an output path for coupling data from the memory space to the system bus in response to a data read command ;
memory space drivers that accesses data locations within the memory space (141) and that couple contents of selected ones of the data locations to the output path in response to a data read command ;
a clock mechanism (127) that provides a clock signal (129) to synchronize internal operations of said memory device (105) ;
a buffer (153) that stores a number of clock pulses ;
and a delay mechanism (121) coupled to the buffer (153) , the delay mechanism (121) causing delay of at least one of said output path and said memory space drivers by an amount corresponding the number of clock pulses ;
wherein said device is adapted for synchronization with other memory (first usage, first usage map, usage map updating module) elements (105) , in response to the controller (103) causing the buffer (153) to be loaded with a number that causes equalization of command response time for said device to the desired response time .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		JPH1173311A

Filed: 1997-08-29     Issued: 1999-03-16

コンピュータ・システムにおける記憶媒体に記憶された情報のアクセス及び変更を制御する方法及び装置

(Original Assignee) Vercon Ltd; バーコン リミテッド     

Robb David, Jackson White Norman, Killian Reginald, ロッブ デビッド, ジャクソン ホワイト ノーマン, キリアン リジナルド
US6618736B1
CLAIM 1 . A method for file system (フォーマット) creation and archival comprising : providing a first set (アップ, エリア) of storage units and a second set (アップ, エリア) of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 5 【請求項５】 前記コンピュータ・システムの中央処理 装置（ＣＰＵ）から独立し、かつそのユーザにアクセス 不能にされたスーパバイザ手段（スーパバイザ）が設け られ、 前記管理手段は、セクタから読み出されるか又はセクタ に書き込まれる情報がオペレーティング・システム情報 であるか又はユーザ情報であるか、前記セクタが前記ブ ート・パーティションにあるか又は一般パーティション にあるか、及び前記パーティションは活性であるか又は 不活性であるかに従って、前記記憶媒体上での読み出し ／書き込み動作を許可し、規制し、又は禁止し、 前記管理手段は、活性な一般パーティション上でのみの フォーマット (file systems, file system) 動作を許可し、かつ前記ブート・パーティ ション上で又は不活性な一般パーティション上でフォー マット動作を禁止し、 かつ、禁止された読み出し、書き込み又はフォーマット 動作を実行したときはユーザに警告を発生する前記いず れかの請求項記載の方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (アップ, エリア) of storage units is stored in a local storage device (少なくとも) and the second set (アップ, エリア) of storage units is stored in a remote storage device . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the second set (アップ, エリア) contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (アップ, エリア) contain valid data . 		JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ, エリア) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (アップ, エリア) contains valid data , reading the data item from the corresponding storage unit of the second set . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ, エリア) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (アップ, エリア) does not contain valid data , reading the data item from the storage unit of the first set . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (アップ, エリア) of storage units , each storage unit (少なくとも) of the third set corresponding to one of the storage units of the first set (アップ, エリア) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the third set (アップ, エリア) contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (アップ, エリア) contain valid data . 		JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ, エリア) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (アップ, エリア) contains valid data , reading the data item from the corresponding storage unit of the third set . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ, エリア) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (アップ, エリア) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (アップ, エリア) contains valid data , reading the data item from the corresponding storage unit of the second set . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ, エリア) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (アップ, エリア) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (アップ, エリア) does not contain valid data , reading the data item from the storage unit of the first set . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (少なくとも) of the second set (アップ, エリア) for which an indication of valid data is stored in the first usage map . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (アップ, エリア) of storage units with the third set (アップ, エリア) of storage units . 		JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (アップ, エリア) that contain valid data to those corresponding storage units of the third set (アップ, エリア) that do not contain valid data ;

and for each storage unit (少なくとも) of the second set that is copied , storing an indication of valid data in the second usage map . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 17 . A method for creating and archiving file systems (フォーマット) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (アップ, エリア) of private storage units , each of the private storage units corresponding to a shared storage unit (少なくとも) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 5 【請求項５】 前記コンピュータ・システムの中央処理 装置（ＣＰＵ）から独立し、かつそのユーザにアクセス 不能にされたスーパバイザ手段（スーパバイザ）が設け られ、 前記管理手段は、セクタから読み出されるか又はセクタ に書き込まれる情報がオペレーティング・システム情報 であるか又はユーザ情報であるか、前記セクタが前記ブ ート・パーティションにあるか又は一般パーティション にあるか、及び前記パーティションは活性であるか又は 不活性であるかに従って、前記記憶媒体上での読み出し ／書き込み動作を許可し、規制し、又は禁止し、 前記管理手段は、活性な一般パーティション上でのみの フォーマット (file systems, file system) 動作を許可し、かつ前記ブート・パーティ ション上で又は不活性な一般パーティション上でフォー マット動作を禁止し、 かつ、禁止された読み出し、書き込み又はフォーマット 動作を実行したときはユーザに警告を発生する前記いず れかの請求項記載の方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (フォーマット) of each server comprises a combination of the set of shared storage units and the first set (アップ, エリア) of private storage units for the server . 		JPH1173311A
CLAIM 5 【請求項５】 前記コンピュータ・システムの中央処理 装置（ＣＰＵ）から独立し、かつそのユーザにアクセス 不能にされたスーパバイザ手段（スーパバイザ）が設け られ、 前記管理手段は、セクタから読み出されるか又はセクタ に書き込まれる情報がオペレーティング・システム情報 であるか又はユーザ情報であるか、前記セクタが前記ブ ート・パーティションにあるか又は一般パーティション にあるか、及び前記パーティションは活性であるか又は 不活性であるかに従って、前記記憶媒体上での読み出し ／書き込み動作を許可し、規制し、又は禁止し、 前記管理手段は、活性な一般パーティション上でのみの フォーマット (file systems, file system) 動作を許可し、かつ前記ブート・パーティ ション上で又は不活性な一般パーティション上でフォー マット動作を禁止し、 かつ、禁止された読み出し、書き込み又はフォーマット 動作を実行したときはユーザに警告を発生する前記いず れかの請求項記載の方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (アップ, エリア) of private storage units and the first usage map of a first server . 		JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (フォーマット) for a second server using the stored template . 		JPH1173311A
CLAIM 5 【請求項５】 前記コンピュータ・システムの中央処理 装置（ＣＰＵ）から独立し、かつそのユーザにアクセス 不能にされたスーパバイザ手段（スーパバイザ）が設け られ、 前記管理手段は、セクタから読み出されるか又はセクタ に書き込まれる情報がオペレーティング・システム情報 であるか又はユーザ情報であるか、前記セクタが前記ブ ート・パーティションにあるか又は一般パーティション にあるか、及び前記パーティションは活性であるか又は 不活性であるかに従って、前記記憶媒体上での読み出し ／書き込み動作を許可し、規制し、又は禁止し、 前記管理手段は、活性な一般パーティション上でのみの フォーマット (file systems, file system) 動作を許可し、かつ前記ブート・パーティ ション上で又は不活性な一般パーティション上でフォー マット動作を禁止し、 かつ、禁止された読み出し、書き込み又はフォーマット 動作を実行したときはユーザに警告を発生する前記いず れかの請求項記載の方法。
US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device (少なくとも) and the private storage units are stored in a remote storage device . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。
US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (少なくとも) contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。
US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。
US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。
US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (アップ, エリア) of private storage units , each private storage unit (少なくとも) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (少なくとも) of the second set (アップ, エリア) contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (アップ, エリア) contain valid data . 		JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (アップ, エリア) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (アップ, エリア) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (アップ, エリア) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (アップ, エリア) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (アップ, エリア) does not contain valid data , reading the data item from the shared storage unit . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (少なくとも) of the first set (アップ, エリア) for which an indication of valid data is stored in the first usage map . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (アップ, エリア) of private storage units with the second set (アップ, エリア) of private storage units . 		JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (アップ, エリア) that contain valid data to those corresponding private storage units of the second set (アップ, エリア) that do not contain valid data ;

and for each private storage unit (少なくとも) of the first set that is copied , storing an indication of valid data in the second usage map . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 36 . A system for creating and archiving a file system (フォーマット) within at least one storage device comprising a first set (アップ, エリア) of storage units and a second set (アップ, エリア) of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 5 【請求項５】 前記コンピュータ・システムの中央処理 装置（ＣＰＵ）から独立し、かつそのユーザにアクセス 不能にされたスーパバイザ手段（スーパバイザ）が設け られ、 前記管理手段は、セクタから読み出されるか又はセクタ に書き込まれる情報がオペレーティング・システム情報 であるか又はユーザ情報であるか、前記セクタが前記ブ ート・パーティションにあるか又は一般パーティション にあるか、及び前記パーティションは活性であるか又は 不活性であるかに従って、前記記憶媒体上での読み出し ／書き込み動作を許可し、規制し、又は禁止し、 前記管理手段は、活性な一般パーティション上でのみの フォーマット (file systems, file system) 動作を許可し、かつ前記ブート・パーティ ション上で又は不活性な一般パーティション上でフォー マット動作を禁止し、 かつ、禁止された読み出し、書き込み又はフォーマット 動作を実行したときはユーザに警告を発生する前記いず れかの請求項記載の方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (アップ, エリア) of storage units is stored in a local storage device (少なくとも) and the second set (アップ, エリア) of storage units is stored in a remote storage device . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the second set (アップ, エリア) contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (アップ, エリア) contain valid data . 		JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ, エリア) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (アップ, エリア) contains valid data , to read the data item from the corresponding storage unit of the second set . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ, エリア) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (アップ, エリア) does not contain valid data , to read the data item from the storage unit of the first set . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (アップ, エリア) of storage units , each storage unit (少なくとも) of the third set corresponding to one of the storage units of the first set (アップ, エリア) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (少なくとも) of the first set (アップ, エリア) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (アップ, エリア) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the third set (アップ, エリア) contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (アップ, エリア) contain valid data . 		JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ, エリア) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (アップ, エリア) contains valid data , to read the data item from the corresponding storage unit of the third set . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ, エリア) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (アップ, エリア) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (アップ, エリア) contains valid data , to read the data item from the corresponding storage unit of the second set . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set (アップ, エリア) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (アップ, エリア) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (アップ, エリア) does not contain valid data , to read the data item from the storage unit of the first set . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (少なくとも) of the second set (アップ, エリア) for which an indication of valid data is stored in the first usage map . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (アップ, エリア) of storage units with the third set (アップ, エリア) of storage units . 		JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (アップ, エリア) that contain valid data to those corresponding storage units of the third set (アップ, エリア) that do not contain valid data ;

and wherein the storage unit (少なくとも) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。
US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (フォーマット) within at least one storage device comprising a first set (アップ, エリア) of storage units and a second set (アップ, エリア) of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH1173311A
CLAIM 1 【請求項１】 コンピュータ・システムの一部を形成す る記憶媒体上に記憶した情報のアクセス及び変更を制御 する方法であって、 前記記憶媒体に記憶された情報をブート・パーティショ ン及び少なくとも (storage unit, local storage device) 一つの一般パーティションを含む重複 しない複数のパーティションに分割することを含む方法 において、 前記パーティションのうちの一つを多数回復可能書き込 み（ＷＭＲ）パーティションに指定し、もし書き込みコ マンドが更新情報により一つの又は前記ＷＭＲパーティ ションに記憶されている残留情報に重ね書きするように 発行されたときは、残りのセッション中の要求に従って 前記更新情報をアクセスできるように、任意の残留情報 が記憶され、かつ前記更新情報に対する（仮想）ポイン タが設定又は保持されている位置以外の位置に、前記更 新情報を書き込むことを特徴とするコンピュータ・シス テムの一部を形成する記憶媒体に記憶したアクセス及び 変更を制御する方法。

JPH1173311A
CLAIM 5 【請求項５】 前記コンピュータ・システムの中央処理 装置（ＣＰＵ）から独立し、かつそのユーザにアクセス 不能にされたスーパバイザ手段（スーパバイザ）が設け られ、 前記管理手段は、セクタから読み出されるか又はセクタ に書き込まれる情報がオペレーティング・システム情報 であるか又はユーザ情報であるか、前記セクタが前記ブ ート・パーティションにあるか又は一般パーティション にあるか、及び前記パーティションは活性であるか又は 不活性であるかに従って、前記記憶媒体上での読み出し ／書き込み動作を許可し、規制し、又は禁止し、 前記管理手段は、活性な一般パーティション上でのみの フォーマット (file systems, file system) 動作を許可し、かつ前記ブート・パーティ ション上で又は不活性な一般パーティション上でフォー マット動作を禁止し、 かつ、禁止された読み出し、書き込み又はフォーマット 動作を実行したときはユーザに警告を発生する前記いず れかの請求項記載の方法。

JPH1173311A
CLAIM 22 【請求項２２】 読み出し、書き込み及びフォーマット 動作の実行の規制又は阻止は、前記記憶媒体のセット・ アップ (first set, second set, third set) 又は保守できるように解除され、かつその後に再 復帰可能にされている請求項２１記載の方法。

JPH1173311A
CLAIM 24 【請求項２４】 前記記憶媒体はファイルサーバであ り、前記コンピュータ・システムはローカル・エリア (first set, second set, third set) ・ ネットワークであり、かつユーザ・コンピュータにより 禁止された動作を実行するための試行が前記ユーザ・コ ンピュータのリセットを発生させるように、そのユーザ ・コンピュータが前記ファイルサーバのどのパーティシ ョンを決定できるのかを使用している請求項１又は１１ 記載の方法。



US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5887134A

Filed: 1997-06-30     Issued: 1999-03-23

System and method for preserving message order while employing both programmed I/O and DMA operations

(Original Assignee) Sun Microsystems Inc     (Current Assignee) Oracle America Inc

Zahir Ebrahim
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units (same destination node) and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (same destination node) are stored in a same storage device . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (same destination node) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (same destination node) of the second set contain valid data . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (same destination node) , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (same destination node) of the third set contain valid data . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units (same destination node) with the third set of storage units . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (same destination node) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (same destination node) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units (same destination node) and the first set of private storage units for the server . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (same destination node) and the first usage map of a first server . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (same destination node) are stored in a same storage device . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (same destination node) are stored a local storage device and the private storage units are stored in a remote storage device . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (same destination node) contain valid data . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units (same destination node) , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (same destination node) of the second set contain valid data . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (same destination node) with the second set of private storage units . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (same destination node) of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units (same destination node) and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (first subset) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US5887134A
CLAIM 7 . The method of claim 6 , including : each DMA store command specifying a respective source address that is a local virtual address and a respective destination address that is a local physical address ;
each PIO store command specifying a respective destination address that is a local physical address ;
at the first node : establishing an outgoing memory management unit (OMMU) and an incoming memory management unit (IMMU) ;
storing in the OMMU entries , each OMMU entry mapping a specified range of local physical addresses to a corresponding range of global address , each OMMU entry also specifying one of the queues in the first node' ;
s network interface in which to store PIO and DMA store commands whose destination address corresponds the range of local physical addressed mapped thereby ;
storing in the IMMU entries , a first subset (storage unit writing module) of the IMMU entries each mapping a specified range of global addresses to a corresponding range of local physical address , and a second subset of the IMMU entries each mapping a specified range of local virtual addresses to a corresponding range of local physical address ;
at the first node' ;
s network interface : for each received PIO store and DMA store command , locating an OMMU entry in the OMMU corresponding to the respective destination address specified therein , and converting the respective destination address in each received PIO store and DMA store command into a corresponding global address in accordance with the located OMMU entry ;
for each received DMA store command , locating an IMMU entry in the IMMU corresponding to the respective source address specified therein , and converting the respective specified source address into a corresponding local physical address in accordance with the located IMMU entry ;
wherein the packetizing step is performed after said converting steps so that each data transfer packet specifies a global destination address ;
said packetizing step including , for each DMA store command , retrieving data from the local physical address produced by the converting step for the DMA store command .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (same destination node) are stored in a same storage device . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (same destination node) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (same destination node) of the second set contain valid data . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (same destination node) , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5887134A
CLAIM 6 . A method of transmitting messages between nodes of a distributed computer system using a combination of memory mapped programmed I/O (PIO) commands and memory mapped DMA commands to transmit each of a subset of the messages , comprising steps of : establishing a plurality of queues in the first node' ;
s network interface ;
initiating the transmission of a multipart message from a first node to a second node of the distributed computer system by sending to a network interface of the first node a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues ;
at the first node' ;
s network interface : receiving the sequence of PIO and DMA commands corresponding to the multipart message ;
storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
for each queue , packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue , and transmitting each of the ordered stream of data transfer packets to a destination node specified therein , the transmitting step preserving packet order within the ordered stream of data transfer packets , at least with respect to packets being transmitted to a same destination node (storage units) , so as to store the respective components of the multipart message in their respective specified memory locations in the destination node in the predefined message component order .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (same destination node) of the third set contain valid data . 		US5887134A
CLAIM 11 . A network interface for a first node of a distributed computer system , comprising : receive logic for receiving a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of a multipart message to be stored in a respective specified memory mapped location in a second node of the distributed computer system , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
the packetizing means including : a plurality of queues ;
classification logic for assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues and for storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
and packetizing logic , for each queue , for packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue ;
the transmitting means including means for transmitting each of the ordered stream of data transfer packets to a destination node specified therein while preserving packet order within the ordered stream of data transfer packets at least with respect to packets being transmitted to a same destination node (storage units) .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units (same destination node) with the third set of storage units . 		US5887134A
CLAIM 11 . A network interface for a first node of a distributed computer system , comprising : receive logic for receiving a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of a multipart message to be stored in a respective specified memory mapped location in a second node of the distributed computer system , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
the packetizing means including : a plurality of queues ;
classification logic for assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues and for storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
and packetizing logic , for each queue , for packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue ;
the transmitting means including means for transmitting each of the ordered stream of data transfer packets to a destination node specified therein while preserving packet order within the ordered stream of data transfer packets at least with respect to packets being transmitted to a same destination node (storage units) .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (same destination node) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5887134A
CLAIM 11 . A network interface for a first node of a distributed computer system , comprising : receive logic for receiving a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of a multipart message to be stored in a respective specified memory mapped location in a second node of the distributed computer system , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
the packetizing means including : a plurality of queues ;
classification logic for assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues and for storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
and packetizing logic , for each queue , for packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue ;
the transmitting means including means for transmitting each of the ordered stream of data transfer packets to a destination node specified therein while preserving packet order within the ordered stream of data transfer packets at least with respect to packets being transmitted to a same destination node (storage units) .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units (same destination node) and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5887134A
CLAIM 11 . A network interface for a first node of a distributed computer system , comprising : receive logic for receiving a sequence of PIO store and DMA store commands , each PIO store and DMA store command specifying a respective component of a multipart message to be stored in a respective specified memory mapped location in a second node of the distributed computer system , the sequence of the PIO store and DMA store commands corresponding to a predefined message component order ;
the packetizing means including : a plurality of queues ;
classification logic for assigning each of the PIO store and DMA store commands that specify a respective component of the multipart message to a same one of the queues and for storing each PIO and DMA command received by the first node' ;
s network interface in the assigned one of the queues , wherein the PIO and DMA commands stored in each queue are stored in a same order as they are received by the first node' ;
s network interface , which corresponds to the predefined message component order ;
and packetizing logic , for each queue , for packetizing the PIO and DMA commands therein so as to generate an ordered stream of data transfer packets whose order corresponds to the order in which the PIO and DMA commands are stored in the queue ;
the transmitting means including means for transmitting each of the ordered stream of data transfer packets to a destination node specified therein while preserving packet order within the ordered stream of data transfer packets at least with respect to packets being transmitted to a same destination node (storage units) .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5905990A

Filed: 1997-06-23     Issued: 1999-05-18

File system viewpath mechanism

(Original Assignee) International Business Machines Corp     (Current Assignee) Seagate Systems UK Ltd

Scott D. Inglett
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (second sets, first set) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets (second sets, first set) of storage units are stored in a same storage device . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (second sets, first set) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (second sets, first set) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (second sets, first set) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (third set) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (second sets, first set) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (third set) contains valid data . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (third set) contain valid data . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (second sets, first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (third set) contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (second sets, first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (third set) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (second sets, first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (third set) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units with the third set (third set) of storage units . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set (third set) that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (second sets, first set) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (second sets, first set) of private storage units for the server . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (second sets, first set) of private storage units and the first usage map of a first server . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (second sets, first set) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (second sets, first set) does not contain valid data , reading the data item from the shared storage unit . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (second sets, first set) for which an indication of valid data is stored in the first usage map . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (second sets, first set) of private storage units with the second set of private storage units . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (second sets, first set) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (second sets, first set) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets (second sets, first set) of storage units are stored in a same storage device . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (second sets, first set) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (second sets, first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (second sets, first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (third set) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (second sets, first set) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit of the first set (second sets, first set) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (third set) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (third set) contains valid data . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (third set) contain valid data . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (second sets, first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (third set) contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (second sets, first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (third set) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (second sets, first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (third set) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units with the third set (third set) of storage units . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set (third set) that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set (third set) of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US6618736B1
CLAIM 53 . An computer program product (intermediate data) for creating and archiving a file system within at least one storage device comprising a first set (second sets, first set) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5905990A
CLAIM 1 . A file system for a computer having a device for storing data and an operating system for organizing the data into logical file system objects including files and directories , the operating system interacting with the file objects by means of intermediate data (computer program product) structures , the file system comprising : means for creating a mountpoint directory over an existing directory of the file system ;
means for dynamically searching said intermediate data structures to find a requested logical file system object ;
and means for manifesting a representation of the requested logical file system object in said mountpoint directory as a separate logical file system object .

US5905990A
CLAIM 9 . The file system of claim 7 wherein there are at least four of said independent search paths each of a different search-path type including : a regular expression search path instructing said dynamic searching means to search a first set (first set, second sets) of directories for the requested logical file system object based on a regular expression ;
an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name ;
an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension ;
and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension .

US5905990A
CLAIM 14 . A method of manifesting a representation of a requested file object in a computer system , the file object residing in a storage device (data item) and having a corresponding intermediate data structure which is used to access the file object , comprising the steps of : creating a mountpoint directory over an existing directory of the computer system ;
searching the computer system for the intermediate data structure ;
and if the intermediate data structure is found , associating the intermediate data structure with a representation of the requested file as a separate logical file system object but , if the intermediate data structure is not found , indicating that the requested file object does not exist .

US5905990A
CLAIM 18 . The method of claim 17 wherein : there are at least four of said independent search paths each of a different search-path type including a regular expression search path instructing said dynamic searching means to search a first set of directories for the requested logical file system object based on a regular expression , an alternate search path instructing said dynamic searching means to search a second set of directories for the requested logical file system object based on an object name , an extension search path instructing said dynamic searching means to search a third set of directories for the requested logical file system object based on an object name extension , and a library search path instructing said dynamic searching means to search a fourth set of directories for the requested logical file system object without regard to said regular expression , said object name or said object name extension ;
and said searching step first searches said second set of directories , then searches said first set of directories only if the requested logical file system object is not found in the second set of directories , then searches said third set of directories only if the requested file object is not found in the first or second sets (first set, second sets) of directories , and thereafter searches said fourth set of directories only if the requested file object is not found in the first , second or third sets of directories .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5844855A

Filed: 1997-05-16     Issued: 1998-12-01

Method and apparatus for writing to memory components

(Original Assignee) Rambus Inc     (Current Assignee) Rambus Inc

Frederick A. Ware, John B. Dillon, Richard M. Barth, Billy Wayne Garrett, Jr., John Girdner Atwood, Jr., Michael P. Farmwald, Richard DeWitt Crisp
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (time t) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage (time t) map . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (time t) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage (time t) map of a first server . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set for which an indication of valid data is stored in the first usage (time t) map . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (write operation) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5844855A
CLAIM 12 . A method for writing data to a memory component having an array of storage cells arranged in rows and columns , comprising the steps of : the memory component initially receiving on its address lines a row address specifying a row in the storage array to be sensed and held in a set of sense amplifiers ;
and the memory component subsequently performing a first bit masked write operation (storage unit writing module) comprising the steps of : the memory component receiving on address lines a first column address specifying a first column in the storage array ;
the memory component receiving first write data on data lines during the receiving of the first column address ;
the memory component receiving a first bit mask on the data lines prior to the receiving of the first write data ;
and writing the first write data into the array starting at the received first column address in accordance with the first bit mask .

US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (time t) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module (write operation) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5844855A
CLAIM 12 . A method for writing data to a memory component having an array of storage cells arranged in rows and columns , comprising the steps of : the memory component initially receiving on its address lines a row address specifying a row in the storage array to be sensed and held in a set of sense amplifiers ;
and the memory component subsequently performing a first bit masked write operation (storage unit writing module) comprising the steps of : the memory component receiving on address lines a first column address specifying a first column in the storage array ;
the memory component receiving first write data on data lines during the receiving of the first column address ;
the memory component receiving a first bit mask on the data lines prior to the receiving of the first write data ;
and writing the first write data into the array starting at the received first column address in accordance with the first bit mask .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage (time t) map . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (positive integer) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5844855A
CLAIM 8 . The method of claim 1 , wherein the first write data has m bytes of b bits of data , wherein m is a positive integer (storage unit update module) greater than or equal to one and b is a positive integer greater than or equal to eight .

US6618736B1
CLAIM 53 . An computer program product (first input) for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5844855A
CLAIM 43 . The memory system of claim 40 , wherein the memory array has a memory cycle time and the ratio of the number of data inputs of the memory array to the number inputs of the first receiver is the same ratio as the memory array cycle time t (first usage) o a bit transmission rate of the data bus .

US5844855A
CLAIM 45 . The memory system of claim 40 , wherein the control circuitry further comprises : a second receiver configured to receive a plurality of control signals ;
a first multiplexer having a first input (computer program product) coupled to the outputs of the register , a second input coupled to the first receiver , a control input configured to receive one of the plurality of control signals from the second receiver , and an output coupled to the mask inputs ;
and a second multiplexer having a first input coupled to the outputs of the register , a second input coupled to the first receiver , a control input configured to receive one of the plurality of control signals from the second receiver , and an output coupled to the data inputs .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5901327A

Filed: 1997-03-17     Issued: 1999-05-04

Bundling of write data from channel commands in a command chain for transmission over a data link between data storage systems for remote data mirroring

(Original Assignee) EMC Corp     (Current Assignee) EMC Corp

Yuval Ofek
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module (write operation) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5901327A
CLAIM 2 . The data storage system as claimed in claim 1 , wherein the chain defines a write operation (storage unit writing module) with respect to a single volume of data storage , and the data storage controller is programmed to commit to the primary data storage and to the remote data storage results of all channel commands in the chain before commitment of results of any following channel command received by the data storage controller from the host computer .

US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit of the first set ;

wherein the storage unit writing module (write operation) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5901327A
CLAIM 2 . The data storage system as claimed in claim 1 , wherein the chain defines a write operation (storage unit writing module) with respect to a single volume of data storage , and the data storage controller is programmed to commit to the primary data storage and to the remote data storage results of all channel commands in the chain before commitment of results of any following channel command received by the data storage controller from the host computer .

US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5901327A
CLAIM 8 . A program storage device (data item) readable by a data storage system , said program storage device encoding a program for execution by the data storage system for controlling operation of the data storage system in a remote copy mode in which the data storage system receives channel commands from a host computer , and the data storage system stores write data from the channel commands in primary data storage of the data storage system and transmits the write data over a data link to remote data storage , wherein the program is executable by the data storage system for receiving a chain of a plurality of the channel commands from the host computer , bundling the write data for all write commands in the chain into a bundle of write data for transmission over the data link to the remote data storage , decoding the channel commands in the chain to determine when the data storage controller has received a last channel command in the chain , and once the data storage controller has received the last channel command in the chain , transmitting the bundle of write data over the data link to the remote data storage .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0800135A1

Filed: 1997-03-11     Issued: 1997-10-08

Method and apparatus for controlling access to and corruption of information in computer systems

(Original Assignee) Arendee Ltd     (Current Assignee) Arendee Ltd

Norman Jackson White, David Robb, Reginald Killean
US6618736B1
CLAIM 1 . A method for file system creation (updated information) and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit (write operation, floppy disk, hard disk) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0800135A1
CLAIM 1 A method of controlling access to and modification of information stored on a storage medium forming part of a computer system comprising :    dividing information stored on the storage medium into a plurality of non-overlapping partitions including a boot partition and at least one general partition , characterised by    designating at least one of said partitions a Write Many Recoverable (WMR) partition wherein , in use , if a write command is issued to overwrite any resident information stored in a/the WMR partition by updated information (file system creation) , the updated information is written on the storage medium in a location other than where any resident information is stored and a (virtual) pointer to the updated information is set up/kept so that the updated information can be accessed , as required during a remainder of a session .

EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (write operation, floppy disk, hard disk) . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (write operation, floppy disk, hard disk) of the second set contains valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (write operation, floppy disk, hard disk) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (write operation, floppy disk, hard disk) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (write operation, floppy disk, hard disk) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (write operation, floppy disk, hard disk) of the third set contains valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (write operation, floppy disk, hard disk) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (write operation, floppy disk, hard disk) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (write operation, floppy disk, hard disk) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (write operation, floppy disk, hard disk) of the second set for which an indication of valid data is stored in the first usage map . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (write operation, floppy disk, hard disk) of the second set that is copied , storing an indication of valid data in the second usage map . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (write operation, floppy disk, hard disk) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (write operation, floppy disk, hard disk) . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (write operation, floppy disk, hard disk) contains valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (write operation, floppy disk, hard disk) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (write operation, floppy disk, hard disk) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (write operation, floppy disk, hard disk) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (write operation, floppy disk, hard disk) of the second set contains valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (write operation, floppy disk, hard disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (write operation, floppy disk, hard disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (write operation, floppy disk, hard disk) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (write operation, floppy disk, hard disk) of the first set for which an indication of valid data is stored in the first usage map . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (write operation, floppy disk, hard disk) of the first set that is copied , storing an indication of valid data in the second usage map . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (write operation, floppy disk, hard disk) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (write operation, floppy disk, hard disk) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (write operation, floppy disk, hard disk) . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (write operation, floppy disk, hard disk) of the second set contains valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (write operation, floppy disk, hard disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (write operation, floppy disk, hard disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (write operation, floppy disk, hard disk) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (write operation, floppy disk, hard disk) of the first set ;

wherein the storage unit writing module (write operation, floppy disk, hard disk) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (write operation, floppy disk, hard disk) of the third set contains valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (write operation, floppy disk, hard disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (write operation, floppy disk, hard disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (write operation, floppy disk, hard disk) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (write operation, floppy disk, hard disk) of the second set for which an indication of valid data is stored in the first usage map . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (write operation, floppy disk, hard disk) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (write operation, floppy disk, hard disk) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0800135A1
CLAIM 5 A method as claimed in any preceding claim , wherein there is also provided supervising means (a Supervisor) separate of a central processing unit (CPU) of the computer system and made inaccessible to the user , said supervising means allowing/restricting/ prohibiting read/write operation (storage unit writing module, storage unit, remote storage device, storage unit update module) s uopon the storage medium depending upon whether information to be read from a sector or written to a sector is operating system information or user information , whether the sector is in the boot partition or in a general partition , and whether the partition is active or inactive , said supervising means also allowing a format operation only on a general partition which is active and prohibiting a format operation on the boot partition or on a general partition which is inactive , and causing a warning to be issued to the user should an attempt be made to perform a prohibited read , write or format operation .

EP0800135A1
CLAIM 23 A method as claimed in claims 1 or 11 , wherein the storage medium may be selected from any one of a hard disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , a floppy disk (storage unit writing module, storage unit, remote storage device, storage unit update module) , an optical disk or a tape .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5796624A

Filed: 1997-02-06     Issued: 1998-08-18

Method and apparatus for designing circuits for wave pipelining

(Original Assignee) Research Foundation of State University of New York     (Current Assignee) Research Foundation of State University of New York

Ramalingam Sridhar, Zhang Xuguang
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage (high value) map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage (high value) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage (high value) map comprises : initializing the second usage map to indicate that none of the storage units of the third set contain valid data . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage (high value) map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage (high value) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage (high value) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage (high value) map . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage (high value) map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage (high value) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set contains valid data . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage (high value) map comprises : initializing the second usage map to indicate that none of the private storage units of the second set contain valid data . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (high value) map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (high value) map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (high value) map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage (high value) map . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage (high value) map for indicating which storage units of third set contain valid data . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage (high value) map that the corresponding storage unit of the third set contains valid data . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage (high value) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage (high value) map is initially reset to indicate that none of the storage units of the third set contain valid data . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (high value) map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (high value) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (high value) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage (high value) map . 		US5796624A
CLAIM 1 . A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern , the method comprising the steps : forming a map of the desired logic function ;
assigning cells of the map into pairs of map cells ;
implementing a transmission gate for each one , if any , of the pairs of map cells that has one high value (second usage, second usage map) and one low value ;
implementing a pull transistor for each one , if any , of the pairs of map cells having values that are equal ;
and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern .

US6618736B1
CLAIM 53 . An computer program product (first input) for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5796624A
CLAIM 6 . The method according to claim 1 , further comprising the steps of : for the transmission gate , if any , coupling a first terminal to a first input (computer program product) signal , coupling a second terminal to a node , and coupling a gate to a second input signal ;
for the pull transistor , if any , coupling a first terminal to a voltage source , coupling a second terminal to the node , and coupling a gate to a third input signal ;
and implementing a driver coupled to the node , the driver amplifying a voltage , adjusting logic levels , and providing an output signal , wherein each one of a plurality of paths to the output signal from the first input signal , the second input signal and the third input signal , respectively , has substantially equal delays , each one of the paths passing through the driver and one or more of the transmission gate and the pull transistor .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5878408A

Filed: 1996-12-06     Issued: 1999-03-02

Data management system and process

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Gary Alan Van Huben, Joseph Lawrence Mueller, Michael Steven Siegel, Thomas Bernard Warnock, Darryl James McDonald
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (input file) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (input file) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (input file) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (input file) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (input file) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (input file) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (input file) contains valid data . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (input file) contain valid data . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (input file) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (input file) contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (input file) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (input file) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (input file) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (input file) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units with the third set (input file) of storage units . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set (input file) that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (input file) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (input file) of private storage units for the server . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (input file) of private storage units and the first usage map of a first server . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (input file) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (input file) does not contain valid data , reading the data item from the shared storage unit . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (input file) for which an indication of valid data is stored in the first usage map . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (input file) of private storage units with the second set of private storage units . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (input file) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (input file) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (input file) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (input file) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (input file) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (input file) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (input file) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (input file) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (input file) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (input file) contains valid data . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (input file) contain valid data . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (input file) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (input file) contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (input file) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (input file) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (input file) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (input file) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units with the third set (input file) of storage units . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set (input file) that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .

US6618736B1
CLAIM 53 . An computer program product (first method) for creating and archiving a file system within at least one storage device comprising a first set (input file) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5878408A
CLAIM 2 . A data management system for file and database management according to claim 1 wherein said library manager enables two methods for initiating a library process , a first method (computer program product) being library initiated processing , and a second method being designer initiated library processing .

US5878408A
CLAIM 7 . A data management system for file and database management according to claim 3 where a Library Process is pre-checked in the foreground for ensuring the existance of all the required input file (first set, third set) s prior to subjecting the input files to the background processing .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5835953A

Filed: 1996-11-08     Issued: 1998-11-10

Backup system that takes a snapshot of the locations in a mass storage device that has been identified for updating prior to updating

(Original Assignee) Vinca Corp     (Current Assignee) EMC Corp

Richard Ohran
US6618736B1
CLAIM 1 . A method for file system (temporary storage means, consistent state) creation (temporary storage means, consistent state) and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit (stores data) of the first set corresponding to a storage unit of the second set ;

providing a first usage (time t) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (temporary storage means, consistent state) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (stores data) of the second set contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (temporary storage means, consistent state) from a storage unit (stores data) of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (temporary storage means, consistent state) from a storage unit (stores data) of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (stores data) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (temporary storage means, consistent state) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (stores data) of the third set contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (temporary storage means, consistent state) from a storage unit (stores data) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (temporary storage means, consistent state) from a storage unit (stores data) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (temporary storage means, consistent state) from a storage unit (stores data) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (stores data) of the second set for which an indication of valid data is stored in the first usage (time t) map . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (stores data) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (temporary storage means, consistent state) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (stores data) ;

and providing a first usage (time t) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (temporary storage means, consistent state) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (temporary storage means, consistent state) of each server comprises a combination of the set of shared storage units and the first set of private storage units for the server . 		US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage (time t) map of a first server . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (temporary storage means, consistent state) for a second server using the stored template . 		US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (stores data) contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (temporary storage means, consistent state) from a shared storage unit (stores data) ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (temporary storage means, consistent state) from a shared storage unit (stores data) ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (stores data) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (temporary storage means, consistent state) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (stores data) of the second set contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (temporary storage means, consistent state) from a shared storage unit (stores data) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (temporary storage means, consistent state) from a shared storage unit (stores data) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (temporary storage means, consistent state) from a shared storage unit (stores data) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (stores data) of the first set for which an indication of valid data is stored in the first usage (time t) map . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (stores data) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (temporary storage means, consistent state) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (stores data) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (temporary storage means, consistent state) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (stores data) of the second set contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (time t) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (temporary storage means, consistent state) from a storage unit (stores data) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (temporary storage means, consistent state) from a storage unit (stores data) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (stores data) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (temporary storage means, consistent state) to a storage unit (stores data) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (stores data) of the third set contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (temporary storage means, consistent state) from a storage unit (stores data) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (temporary storage means, consistent state) from a storage unit (stores data) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (temporary storage means, consistent state) from a storage unit (stores data) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (stores data) of the second set for which an indication of valid data is stored in the first usage (time t) map . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (stores data) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time to a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (temporary storage means, consistent state) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (stores data) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (temporary storage means, consistent state) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5835953A
CLAIM 1 . In a computer system comprising a primary system having a mass storage system that stores data (storage unit, storage unit reading module) blocks in a plurality of storage locations each having a unique address , and a preservation memory means for providing a snapshot storage location , and wherein said computer system further comprises a backup system having a backup storage location , a method of backing up data blocks that are changed during a first time period that runs from a first instant in time t (first usage) o a second instant in time while reducing the amount of data that must be sent to the backup system , the method comprising the steps of : identifying during a first time period that runs from a first instant in time to a second instant in time , only those storage locations of said mass storage system that have changed by virtue of new data stored in them during said first time period ;
during a second time period that runs from the second instant in time to a third instant in time , when a data block that was stored at said second instant in time in any of said identified storage locations is to be changed , preserving in said preservation memory means a snapshot of the unchanged data block before said data block is changed so that the unchanged data blocks stored in said preservation memory means can be retrieved even though new data is written to said mass storage system after said second instant in time ;
and retrieving during said second time period the unchanged data blocks stored in said preservation memory means and transferring the retrieved data blocks to the backup storage location of the backup system .

US5835953A
CLAIM 6 . A method of backing up data blocks as recited in claim 1 further comprising the steps of : the backup system storing the transferred data blocks in a temporary storage means (file system creation, file system, data item, file systems) until all data blocks to be transferred are received , and after all data blocks to be transferred are received , then the backup system applying the transferred data blocks to a backup storage means that includes all changes made prior to said first instant in time in order to bring the backup storage means current to said second instant of time .

US5835953A
CLAIM 14 . A computer-readable medium as recited in claim 12 wherein said computer-executable instructions further comprise means for determining when a logically consistent state (file system creation, file system, data item, file systems) has been achieved by said mass storage means so that said static snapshot preserves said logically consistent state .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0767431A1

Filed: 1996-10-04     Issued: 1997-04-09

System for backing up computer disk volumes

(Original Assignee) STAC Inc     (Current Assignee) STAC Inc

John E. G. Matze, Douglas L. Whiting
US6618736B1
CLAIM 1 . A method for file system (temporary storage means) creation (temporary storage means) and archival comprising : providing a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

EP0767431A1
CLAIM 42 The method of any of claims 21-26 wherein writes to said disk volume are allowed by caching said writes to a temporary storage means (file system creation, file system) .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (following steps) are stored in a same storage device . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (following steps) is stored in a local storage device and the second set (following steps) of storage units is stored in a remote storage device . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (following steps) contains valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (following steps) of the second set (following steps) contain valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , reading the data item from the storage unit of the first set . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (following steps) , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (following steps) of the third set contain valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , reading the data item from the storage unit of the first set . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (following steps) for which an indication of valid data is stored in the first usage map . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (following steps) of storage units (following steps) with the third set of storage units . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (following steps) of the second set (following steps) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (following steps) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (temporary storage means) of each server comprises a combination of the set of shared storage units (following steps) and the first set of private storage units for the server . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

EP0767431A1
CLAIM 42 The method of any of claims 21-26 wherein writes to said disk volume are allowed by caching said writes to a temporary storage means (file system creation, file system) .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (following steps) and the first usage map of a first server . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (temporary storage means) for a second server using the stored template . 		EP0767431A1
CLAIM 42 The method of any of claims 21-26 wherein writes to said disk volume are allowed by caching said writes to a temporary storage means (file system creation, file system) .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (following steps) are stored in a same storage device . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (following steps) are stored a local storage device and the private storage units are stored in a remote storage device . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (following steps) contain valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (following steps) of private storage units (following steps) , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (following steps) contains valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (following steps) of the second set (following steps) contain valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (following steps) with the second set (following steps) of private storage units . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (following steps) of the first set that contain valid data to those corresponding private storage units of the second set (following steps) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (temporary storage means) within at least one storage device comprising a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

EP0767431A1
CLAIM 42 The method of any of claims 21-26 wherein writes to said disk volume are allowed by caching said writes to a temporary storage means (file system creation, file system) .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (following steps) are stored in a same storage device . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (following steps) is stored in a local storage device and the second set (following steps) of storage units is stored in a remote storage device . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (following steps) contains valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (following steps) of the second set (following steps) contain valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0767431A1
CLAIM 1 A method for backing up data in a computer system from a primary storage means to a backup storage means on a sector-by-sector basis and restoring data in a computer system from said backup storage means to a restore storage means on a sector-by-sector basis , said method comprising the steps of : reading a set of logically contiguous sectors from the primary storage means using a software call of the operating system that provides access (storage unit reading module, storage unit update module) to the files stored on said primary storage means , said call of said operating system performing any physical level remapping necessary to avoid previously detected physical flaws on said primary storage means , writing said set of logically contiguous sectors to said backup storage means , creating a partition on said restore storage means of a size at least as large as the size of said primary storage means , reading a set of logically contiguous sectors from a location on said backup storage means , writing said set of logically contiguous sectors to said partition of said restore storage means using a software call to the operating system that provides access to the files stored on said partition of said restore storage means , said call of said operating system performing any physical level remapping necessary to detect and avoid physical flaws on said restore storage means .

EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , to read the data item from the storage unit of the first set . 		EP0767431A1
CLAIM 1 A method for backing up data in a computer system from a primary storage means to a backup storage means on a sector-by-sector basis and restoring data in a computer system from said backup storage means to a restore storage means on a sector-by-sector basis , said method comprising the steps of : reading a set of logically contiguous sectors from the primary storage means using a software call of the operating system that provides access (storage unit reading module, storage unit update module) to the files stored on said primary storage means , said call of said operating system performing any physical level remapping necessary to avoid previously detected physical flaws on said primary storage means , writing said set of logically contiguous sectors to said backup storage means , creating a partition on said restore storage means of a size at least as large as the size of said primary storage means , reading a set of logically contiguous sectors from a location on said backup storage means , writing said set of logically contiguous sectors to said partition of said restore storage means using a software call to the operating system that provides access to the files stored on said partition of said restore storage means , said call of said operating system performing any physical level remapping necessary to detect and avoid physical flaws on said restore storage means .

EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (following steps) , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (following steps) of the third set contain valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		EP0767431A1
CLAIM 1 A method for backing up data in a computer system from a primary storage means to a backup storage means on a sector-by-sector basis and restoring data in a computer system from said backup storage means to a restore storage means on a sector-by-sector basis , said method comprising the steps of : reading a set of logically contiguous sectors from the primary storage means using a software call of the operating system that provides access (storage unit reading module, storage unit update module) to the files stored on said primary storage means , said call of said operating system performing any physical level remapping necessary to avoid previously detected physical flaws on said primary storage means , writing said set of logically contiguous sectors to said backup storage means , creating a partition on said restore storage means of a size at least as large as the size of said primary storage means , reading a set of logically contiguous sectors from a location on said backup storage means , writing said set of logically contiguous sectors to said partition of said restore storage means using a software call to the operating system that provides access to the files stored on said partition of said restore storage means , said call of said operating system performing any physical level remapping necessary to detect and avoid physical flaws on said restore storage means .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0767431A1
CLAIM 1 A method for backing up data in a computer system from a primary storage means to a backup storage means on a sector-by-sector basis and restoring data in a computer system from said backup storage means to a restore storage means on a sector-by-sector basis , said method comprising the steps of : reading a set of logically contiguous sectors from the primary storage means using a software call of the operating system that provides access (storage unit reading module, storage unit update module) to the files stored on said primary storage means , said call of said operating system performing any physical level remapping necessary to avoid previously detected physical flaws on said primary storage means , writing said set of logically contiguous sectors to said backup storage means , creating a partition on said restore storage means of a size at least as large as the size of said primary storage means , reading a set of logically contiguous sectors from a location on said backup storage means , writing said set of logically contiguous sectors to said partition of said restore storage means using a software call to the operating system that provides access to the files stored on said partition of said restore storage means , said call of said operating system performing any physical level remapping necessary to detect and avoid physical flaws on said restore storage means .

EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , to read the data item from the storage unit of the first set . 		EP0767431A1
CLAIM 1 A method for backing up data in a computer system from a primary storage means to a backup storage means on a sector-by-sector basis and restoring data in a computer system from said backup storage means to a restore storage means on a sector-by-sector basis , said method comprising the steps of : reading a set of logically contiguous sectors from the primary storage means using a software call of the operating system that provides access (storage unit reading module, storage unit update module) to the files stored on said primary storage means , said call of said operating system performing any physical level remapping necessary to avoid previously detected physical flaws on said primary storage means , writing said set of logically contiguous sectors to said backup storage means , creating a partition on said restore storage means of a size at least as large as the size of said primary storage means , reading a set of logically contiguous sectors from a location on said backup storage means , writing said set of logically contiguous sectors to said partition of said restore storage means using a software call to the operating system that provides access to the files stored on said partition of said restore storage means , said call of said operating system performing any physical level remapping necessary to detect and avoid physical flaws on said restore storage means .

EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (following steps) for which an indication of valid data is stored in the first usage map . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (following steps) of storage units (following steps) with the third set of storage units . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (following steps) of the second set (following steps) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (provides access) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		EP0767431A1
CLAIM 1 A method for backing up data in a computer system from a primary storage means to a backup storage means on a sector-by-sector basis and restoring data in a computer system from said backup storage means to a restore storage means on a sector-by-sector basis , said method comprising the steps of : reading a set of logically contiguous sectors from the primary storage means using a software call of the operating system that provides access (storage unit reading module, storage unit update module) to the files stored on said primary storage means , said call of said operating system performing any physical level remapping necessary to avoid previously detected physical flaws on said primary storage means , writing said set of logically contiguous sectors to said backup storage means , creating a partition on said restore storage means of a size at least as large as the size of said primary storage means , reading a set of logically contiguous sectors from a location on said backup storage means , writing said set of logically contiguous sectors to said partition of said restore storage means using a software call to the operating system that provides access to the files stored on said partition of said restore storage means , said call of said operating system performing any physical level remapping necessary to detect and avoid physical flaws on said restore storage means .

EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (temporary storage means) within at least one storage device comprising a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0767431A1
CLAIM 14 The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match ,    setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

EP0767431A1
CLAIM 42 The method of any of claims 21-26 wherein writes to said disk volume are allowed by caching said writes to a temporary storage means (file system creation, file system) .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		WO9712321A1

Filed: 1996-09-25     Issued: 1997-04-03

Virus detection and removal apparatus for computer networks

(Original Assignee) Trend Micro, Incorporated     

Eva Chen, Shuang Ji
US6618736B1
CLAIM 1 . A method for file system (data files) creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

WO9712321A1
CLAIM 3 . The system of claim 2 , wherein the proxy server is a FTP proxy server that handles evaluation and transfer of data files (file systems, file system) , and the daemon is an FTP daemon that communicates with a recipient node and transfers data files to the recipient node .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set contains valid data . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the third set contains valid data . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (data files) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		WO9712321A1
CLAIM 3 . The system of claim 2 , wherein the proxy server is a FTP proxy server that handles evaluation and transfer of data files (file systems, file system) , and the daemon is an FTP daemon that communicates with a recipient node and transfers data files to the recipient node .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (data files) of each server comprises a combination of the set of shared storage units and the first set of private storage units for the server . 		WO9712321A1
CLAIM 3 . The system of claim 2 , wherein the proxy server is a FTP proxy server that handles evaluation and transfer of data files (file systems, file system) , and the daemon is an FTP daemon that communicates with a recipient node and transfers data files to the recipient node .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (data files) for a second server using the stored template . 		WO9712321A1
CLAIM 3 . The system of claim 2 , wherein the proxy server is a FTP proxy server that handles evaluation and transfer of data files (file systems, file system) , and the daemon is an FTP daemon that communicates with a recipient node and transfers data files to the recipient node .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (transferring data) . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (data files) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

WO9712321A1
CLAIM 3 . The system of claim 2 , wherein the proxy server is a FTP proxy server that handles evaluation and transfer of data files (file systems, file system) , and the daemon is an FTP daemon that communicates with a recipient node and transfers data files to the recipient node .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set contains valid data . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (transferring data) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the third set contains valid data . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (data files) within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9712321A1
CLAIM 2 . The system of claim 1 , wherein the server includes : a proxy server for receiving data to be transferred , the proxy server scanning the data to be transferred for viruses and controlling transmission of the data to be transferred according to preset handing instructions and the presence of viruses , the proxy server having a data input , a data output and a control output , the data input coupled to receive the data to be transferred ;
and a daemon for transferring data (remote storage device, corresponding storage unit) from the proxy server in response to control signals from the proxy server , the daemon having a control input , a data input and a data output , the control input of the daemon coupled to the control output of the proxy server for receiving control signals , and the data input of the daemon coupled to the data output of the proxy server for receiving the data to be transferred .

WO9712321A1
CLAIM 3 . The system of claim 2 , wherein the proxy server is a FTP proxy server that handles evaluation and transfer of data files (file systems, file system) , and the daemon is an FTP daemon that communicates with a recipient node and transfers data files to the recipient node .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5832515A

Filed: 1996-09-12     Issued: 1998-11-03

Log device layered transparently within a filesystem paradigm

(Original Assignee) Veritas Software Corp     (Current Assignee) Veritas Technologies LLC

Joel E. Ledain, John A. Colgrove, Dan Koren
US6618736B1
CLAIM 1 . A method for file system (storage path) creation (storage path) and archival comprising : providing a first set (respective plurality) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US5832515A
CLAIM 24 . A data storage subsystem providing a write optimized data storage path (file system creation, file system) in a computer system having a main storage device provided to store data blocks at respective main store addresses , said data storage system comprising : a) a log device providing a log structured storage space for a data segment , said log device being coupleable to the computer system to establish a data transfer path between the computer system and said log device ;
and b) a control program , executable by said computer system , providing for the processing of a predetermined data block and a corresponding predetermined main store address into a user data block and transfer of said user data block to said log device for storage in said data segment , and further providing for the transfer of said user data block to said computer system to allow storage of said predetermined data block in said main storage device at said corresponding main store address .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (respective plurality) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (respective plurality) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (respective plurality) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (respective plurality) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (respective plurality) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (respective plurality) contains valid data . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (respective plurality) contain valid data . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (respective plurality) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (respective plurality) contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (respective plurality) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (respective plurality) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (respective plurality) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (respective plurality) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units with the third set (respective plurality) of storage units . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set (respective plurality) that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (data segments, ordered set) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (respective plurality) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5832515A
CLAIM 19 . The data storage subsystem of claim 18 wherein said control program provides for the log ordered reading and writing of data segments (file systems, archiving file systems) , including said translation map data segment and said predetermined data segment , with respect to an ordered set (file systems, archiving file systems) of said plurality of data segment storage locations .

US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (storage path) of each server comprises a combination of the set of shared storage units and the first set (respective plurality) of private storage units for the server . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US5832515A
CLAIM 24 . A data storage subsystem providing a write optimized data storage path (file system creation, file system) in a computer system having a main storage device provided to store data blocks at respective main store addresses , said data storage system comprising : a) a log device providing a log structured storage space for a data segment , said log device being coupleable to the computer system to establish a data transfer path between the computer system and said log device ;
and b) a control program , executable by said computer system , providing for the processing of a predetermined data block and a corresponding predetermined main store address into a user data block and transfer of said user data block to said log device for storage in said data segment , and further providing for the transfer of said user data block to said computer system to allow storage of said predetermined data block in said main storage device at said corresponding main store address .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (respective plurality) of private storage units and the first usage map of a first server . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (storage path) for a second server using the stored template . 		US5832515A
CLAIM 24 . A data storage subsystem providing a write optimized data storage path (file system creation, file system) in a computer system having a main storage device provided to store data blocks at respective main store addresses , said data storage system comprising : a) a log device providing a log structured storage space for a data segment , said log device being coupleable to the computer system to establish a data transfer path between the computer system and said log device ;
and b) a control program , executable by said computer system , providing for the processing of a predetermined data block and a corresponding predetermined main store address into a user data block and transfer of said user data block to said log device for storage in said data segment , and further providing for the transfer of said user data block to said computer system to allow storage of said predetermined data block in said main storage device at said corresponding main store address .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (respective plurality) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (respective plurality) does not contain valid data , reading the data item from the shared storage unit . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (respective plurality) for which an indication of valid data is stored in the first usage map . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (respective plurality) of private storage units with the second set of private storage units . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (respective plurality) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (storage path) within at least one storage device comprising a first set (respective plurality) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US5832515A
CLAIM 24 . A data storage subsystem providing a write optimized data storage path (file system creation, file system) in a computer system having a main storage device provided to store data blocks at respective main store addresses , said data storage system comprising : a) a log device providing a log structured storage space for a data segment , said log device being coupleable to the computer system to establish a data transfer path between the computer system and said log device ;
and b) a control program , executable by said computer system , providing for the processing of a predetermined data block and a corresponding predetermined main store address into a user data block and transfer of said user data block to said log device for storage in said data segment , and further providing for the transfer of said user data block to said computer system to allow storage of said predetermined data block in said main storage device at said corresponding main store address .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (respective plurality) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (respective plurality) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (respective plurality) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (respective plurality) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (respective plurality) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (respective plurality) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (respective plurality) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (respective plurality) contains valid data . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (respective plurality) contain valid data . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (respective plurality) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (respective plurality) contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (respective plurality) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (respective plurality) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (respective plurality) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (respective plurality) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units with the third set (respective plurality) of storage units . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set (respective plurality) that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (storage path) within at least one storage device comprising a first set (respective plurality) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5832515A
CLAIM 20 . A data storage subsystem transparently and selectively providing an optimized write data path for logical data blocks provided by a filesystem of an operating system executable by a computer system that nominally provides for the storage of logical data blocks on a main filesystem disk drive at locations defined by logical data block numbers , said data storage subsystem comprising : a) log device disk drive providing for the storage of a plurality of data segments , each including a respective plurality (first set, third set) of logical data blocks , and wherein said plurality of data segments are stored by said log device disk drive at locations defined by segment numbers ;
and b) a device driver executable in support of said filesystem to organize a plurality of predetermined logical data blocks into a first predetermined data segment and directing the storage of said predetermined data segment to said log device disk drive , said device driver providing for the construction of a location translation map system relating the logical data block numbers of said predetermined logical data blocks to a first predetermined segment number identifying said first predetermined data segment , said device driver supporting the partitioning of said translation map system into map blocks substitutable as logical data blocks within a second predetermined data segment storable by said log device disk drive .

US5832515A
CLAIM 24 . A data storage subsystem providing a write optimized data storage path (file system creation, file system) in a computer system having a main storage device provided to store data blocks at respective main store addresses , said data storage system comprising : a) a log device providing a log structured storage space for a data segment , said log device being coupleable to the computer system to establish a data transfer path between the computer system and said log device ;
and b) a control program , executable by said computer system , providing for the processing of a predetermined data block and a corresponding predetermined main store address into a user data block and transfer of said user data block to said log device for storage in said data segment , and further providing for the transfer of said user data block to said computer system to allow storage of said predetermined data block in said main storage device at said corresponding main store address .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5663661A

Filed: 1996-07-12     Issued: 1997-09-02

Modular bus with single or double parallel termination

(Original Assignee) Rambus Inc     (Current Assignee) Rambus Inc

John B. Dillon, Srinivas Nimmagadda, Alfredo Moncayo
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (first set) of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (current corresponding) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (first set) of storage units is stored in a local storage device and the second set (second set) of storage units is stored in a remote storage device . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (current corresponding) of the second set (second set) contains valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (second set) contain valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first set) ;

and in response to the first usage map indicating that the corresponding storage unit (current corresponding) of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first set) ;

and in response to the first usage map indicating that the corresponding storage unit (current corresponding) of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first set) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (current corresponding) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (current corresponding) of the third set contains valid data . 		US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first set) ;

and in response to the second usage map indicating that the corresponding storage unit (current corresponding) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first set) ;

and in response to the second usage map indicating that the corresponding storage unit (current corresponding) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first set) ;

and in response to the second usage map indicating that the corresponding storage unit (current corresponding) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (second set) of storage units with the third set of storage units . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (second set) that contain valid data to those corresponding storage units (current corresponding) of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (first set) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (first set) of private storage units for the server . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (first set) of private storage units and the first usage map of a first server . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (second set) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (current corresponding) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (second set) contains valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (second set) contain valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first set) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first set) does not contain valid data , reading the data item from the shared storage unit . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (first set) for which an indication of valid data is stored in the first usage map . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (first set) of private storage units with the second set (second set) of private storage units . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (first set) that contain valid data to those corresponding private storage units of the second set (second set) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (first set) of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (current corresponding) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (first set) of storage units is stored in a local storage device and the second set (second set) of storage units is stored in a remote storage device . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (current corresponding) of the second set (second set) contains valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (second set) contain valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (current corresponding) of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (current corresponding) of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first set) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (first set) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (current corresponding) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (current corresponding) of the third set contains valid data . 		US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (current corresponding) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (current corresponding) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (current corresponding) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (second set) of storage units with the third set of storage units . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (second set) that contain valid data to those corresponding storage units (current corresponding) of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (first set) of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (current corresponding) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5663661A
CLAIM 27 . A dual channel modular bus for communicating signals with a removable first module and a removable second module , the bus comprising : a first singly terminated motherboard data net for communicating first data signals between a master and a first set (first set) of motherboard devices , the first set comprising one or more motherboard devices ;
a second singly terminated motherboard data net for communicating second data signals between the master and a second set (second set) of motherboard devices , the second set comprising another one or more motherboard devices ;
a first socket for communicating the first data signals between the first motherboard data net and a first singly terminated module data net of the removable first module , wherein the first motherboard data net and the first module data net are coupled to form a first doubly terminated data net when the removable first module is present ;
a second socket for communicating the second data signals between the second motherboard data net and a second singly terminated module data net of the removable second module , wherein the second motherboard data net and the second module data net are coupled to form a second doubly terminated data net when the removable second module is present .

US5663661A
CLAIM 31 . A method of adjusting a programmable slave output driver current of a slave coupled to a bus for communicating signals with a master and a removable module , the method comprising the steps of : (A) setting a register setting of the master to a first value , wherein the bus couples the master to the slave , wherein the bus is doubly terminated when the removable module is coupled to the bus , wherein the bus is singly terminated when the removable module is not coupled to the bus ;
(B) communicating the register setting from the master to an output driver of the slave , wherein the slave adjusts a slave current corresponding (corresponding storage unit, corresponding storage units) to the register setting , wherein the slave returns a packet to the master ;
(C) comparing a voltage level of the packet to a reference voltage ;
(D) if the voltage level is greater than or equal to the reference voltage , then adjusting the register setting to provide for a greater slave current and repeating steps B) through C) ;
(E) if the voltage level is less than the reference voltage , then : (1) setting the register setting to a final value , wherein the final value corresponds to twice a level of slave current as the present value ;
(2) communicating the register setting from the master to the output driver of the slave .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		WO9729413A2

Filed: 1996-04-15     Issued: 1997-08-14

System and method for achieving network separation

(Original Assignee) Secure Computing Corporation     

Mark P. Gooderum, Trinh Q. Vu, Glenn Andreas
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (first one) of storage units and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (receiving information) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (first one) of storage units is stored in a local storage device and the second set (first one) of storage units is stored in a remote storage device . 		WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (receiving information) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (first one) contains valid data . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (receiving information) map comprises : initializing the first usage map to indicate that none of the storage units of the second set (first one) contain valid data . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set (first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , reading the data item from the storage unit of the first set . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (data objects) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first one) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (data objects) contains valid data . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (data objects) contain valid data . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (data objects) contains valid data , reading the data item from the corresponding storage unit of the third set . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (data objects) does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set (first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (data objects) does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , reading the data item from the storage unit of the first set . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (first one) for which an indication of valid data is stored in the first usage (receiving information) map . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (first one) of storage units with the third set (data objects) of storage units . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (first one) that contain valid data to those corresponding storage units of the third set (data objects) that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (first one) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (receiving information) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (first one) of private storage units for the server . 		WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (first one) of private storage units and the first usage (receiving information) map of a first server . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (receiving information) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (receiving information) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (receiving information) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (receiving information) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (first one) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (first one) contains valid data . 		WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (first one) contain valid data . 		WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (first one) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (first one) does not contain valid data and the first usage (receiving information) map indicating that the corresponding private storage unit of the first set (first one) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (first one) does not contain valid data and the first usage (receiving information) map indicating that the corresponding private storage unit of the first set (first one) does not contain valid data , reading the data item from the shared storage unit . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (first one) for which an indication of valid data is stored in the first usage (receiving information) map . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (first one) of private storage units with the second set (first one) of private storage units . 		WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (first one) that contain valid data to those corresponding private storage units of the second set (first one) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (first one) of storage units and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (receiving information) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (first one) of storage units is stored in a local storage device and the second set (first one) of storage units is stored in a remote storage device . 		WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (receiving information) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (first one) contains valid data . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (receiving information) map is initially reset to indicate that none of the storage units of the second set (first one) contain valid data . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set (first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , to read the data item from the storage unit of the first set . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (data objects) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first one) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (first one) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (data objects) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (data objects) contains valid data . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (data objects) contain valid data . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (data objects) contains valid data , to read the data item from the corresponding storage unit of the third set . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (data objects) does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set (first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (data objects) does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , to read the data item from the storage unit of the first set . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (first one) for which an indication of valid data is stored in the first usage (receiving information) map . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (first one) of storage units with the third set (data objects) of storage units . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (first one) that contain valid data to those corresponding storage units of the third set (data objects) that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		WO9729413A2
CLAIM 4 . The method according to claim 1 , wherein the step of restricting communication includes the steps of : defining a plurality of types ;
assigning each data object to one of the plurality of types , wherein the step of assigning data objects (third set) includes defining type enforcement rules for accesses by processes to said data objects ;
and applying a type enforcement check of accesses by processes to data objects .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (first one) of storage units and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (receiving information) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9729413A2
CLAIM 2 . The method according to claim 1 , wherein the step of restricting communication between processes includes the steps of : limiting each single user process to sending and receiving information (first usage) from only one burb during the lifetime of that process ;
preventing a process from accessing burbs other than the burb to which the process is bound ;
limiting transfer of incoming packets such that incoming packets can only go to processes bound to the burb associated with the network interface the packet arrived on ;
defining a proxy ;
and ensuring that data passing from the first network interface to the second network interface must pass through the proxy before moving from the first burb to the second burb .

WO9729413A2
CLAIM 5 . A secure server , comprising : an operating system kernel ;
a plurality of network interfaces which communicate with the operating system kernel ;
and a plurality of burbs , including a first and a second burb ;
wherein each network interface is assigned to one burb from the plurality of burbs , wherein each burb includes a protocol stack for handling communication across the network interface , wherein each protocol stack is associated with only one burb and wherein communication from a process bound to the first one (first set, second set) burb must pass through a proxy before being sent to the second burb .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		WO9631035A1

Filed: 1996-03-29     Issued: 1996-10-03

Method and apparatus for policy-based alarm notification in a distributed network management environment

(Original Assignee) Cabletron Systems, Inc.     

Lynn R. Poliquin, Russell Arrowsmith, Lundy Lewis, William Tracy
US6618736B1
CLAIM 1 . A method for file system creation (called user) and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9631035A1
CLAIM 25 . The method of claim 17 further comprising the steps of : calling a called user (file system creation) for notification of the critical alarms ;
asking the called user to enter a password when the called user answers : and not notifying the called user of the critical alarms if the password is not a valid password .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets (time interval) of storage units are stored in a same storage device . 		WO9631035A1
CLAIM 22 . The method of claim 17 wherein , the step of notifying includes the steps of : the user specifying predetermined time interval (second sets) s for automatic notification of the critical alarms ;
and automatically notifying the user at the predetermined time intervals .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets (time interval) of storage units are stored in a same storage device . 		WO9631035A1
CLAIM 22 . The method of claim 17 wherein , the step of notifying includes the steps of : the user specifying predetermined time interval (second sets) s for automatic notification of the critical alarms ;
and automatically notifying the user at the predetermined time intervals .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		WO9716911A1

Filed: 1996-03-20     Issued: 1997-05-09

Secured gateway interface

(Original Assignee) International Business Machines Corporation; Ibm United Kingdom Limited     

Robert Cecil Gore, John Frederick Haugh
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (second communication port) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets (second pass, first pass) of storage units are stored in a same storage device . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first pass (second sets) word and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second pass (second sets) word and a second communication port ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (second communication port) of the second set contains valid data . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (second communication port) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (second communication port) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (second communication port) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (second communication port) of the third set contains valid data . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (second communication port) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (second communication port) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (second communication port) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (second communication port) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (second communication port) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets (second pass, first pass) of storage units are stored in a same storage device . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first pass (second sets) word and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second pass (second sets) word and a second communication port ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (second communication port) of the second set contains valid data . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (second communication port) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (second communication port) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (second communication port) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (second communication port) of the third set contains valid data . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (second communication port) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (second communication port) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (second communication port) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code (program code) for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (second communication port) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9716911A1
CLAIM 2 . A method as claimed m claim 1 , further comprising the steps of : (a) reading by the external computer system (310) a first password and first communication port ;
(b) creating by the external computer system a first socket at the first communication port and listening at the first socket for a connect call from the internal computer system (320) ;
(c) reading by the internal computer system a second password and a second communication port (corresponding storage unit) ;
and (d) creating by the internal computer system a second socket at the second communication port and sending a connect call to the external computer system through the second socket , thereby establishing a connection .

WO9716911A1
CLAIM 12 . An article of manufacture , comprising : a computer usable medium having computer readable program code (program code) means embodied therein for causing an internal computer system to allow an external computer system to initiate a transaction request using internal resources without violating a security firewall between the internal computer system and the external computer system , the computer readable program code means in said article of manufacture comprising : computer readable program means for authenticating a connection initiated by the internal computer system between the internal computer system and the external computer system , thereby establishing an authenticated connection ;
computer readable program means for calling by the external computer system a transaction request received by the external computer system ;
m response to calling the transaction request , computer readable program means for creating by the external computer system an original process environment containing process environment variables , and computer readable program means for creating a string comprising the transaction request and the process environment variables for executing the transaction request ;
computer readable program means for transmitting by the external computer system the string to the internal computer system through the authenticated connection ;
computer readable program means for verifying by the internal computer system the transaction request ;
computer readable program means for recreating by the internal computer system the original process environment ;
and computer readable program means for executing by the internal computer system the transaction request , thereby generating an output .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		EP0747829A1

Filed: 1996-03-13     Issued: 1996-12-11

An input/output (I/O) processor providing shared resources for an I/O bus within a computer

(Original Assignee) HP Inc     (Current Assignee) HP Inc

Ali Ezzet
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (temporary storage) to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set contains valid data . 		EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (temporary storage) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (temporary storage) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (temporary storage) to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the third set contains valid data . 		EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (temporary storage) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (temporary storage) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (temporary storage) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (temporary storage) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (transferring data) . 		EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (temporary storage) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (temporary storage) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (temporary storage) to a shared storage unit ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (temporary storage) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (temporary storage) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (temporary storage) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		EP0747829A1
CLAIM 1 A computing system comprising : a host bus (30 ;
100) ;
a host processor (31 , 32 ;
101 , 102) , coupled to the host bus (30 ;
100) ;
an input/output bus (40 ;
110) ;
a bus bridge (34 ;
104) coupled between the input/output bus (40 ;
110) and the host bus (30 ;
100) , the bus bridge (34 ;
104) being used for transferring information between the host bus (30 ;
100) and the input/output bus (40 ;
110) ;
a first input/output interface (41 ;
111) , coupled to the input/output bus (40 ;
110) , which provides an interface between a first external input/output system (46) and the input/output bus (40 ;
110) ;
a second input/out interface (42 ;
112) , coupled to the input/output bus (40 ;
110) , which provides an interface between a second external input/output system (47) and the input/output bus (40 ;
110) ;
and , an input/output processor (43 ;
113) , coupled to the input/output bus (40 ;
110) , the input/output processor (43 ;
113) including an embedded processor (44 ;
124) coupled to a local memory (45 ;
125) , the input/output processor (43 ;
113) controlling data transactions through the first input/output interface (41 ;
111) and the input/output processor (43 ;
113) controlling data transactions through the second input/output interface (42 ;
112) , the local memory (45 ;
125) providing temporary storage (data item) for data transactions throug the first input/output interface (41 ;
111) and for data transactions through the second input/output interface (42 ;
112) .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (temporary storage) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0747829A1
CLAIM 4 A computer system as in one of claims 1 to 3 additionally comprising : a second input/output bus (120) ;
a second bus bridge (105) coupled between the second input/output bus (120) and the host bus (100) , the second bus bridge (105) being used for transferring information between the host bus (100) and the second input/output bus (120) , and a third input/output interface (121 , 122) , coupled to the second input/output bus (120) , which provides an interface between a third external input/output system and the second input/output bus (120) ;
   wherein the input/output processor (113) , is also coupled to the second input/output bus (120) , the input/output processor (113) controlling data transactions through the third input/output interface (121 , 122) , the local memory (125) providing temporary storage (data item) for data transactions through the third input/output interface (121 , 122) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set contains valid data . 		EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (temporary storage) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0747829A1
CLAIM 4 A computer system as in one of claims 1 to 3 additionally comprising : a second input/output bus (120) ;
a second bus bridge (105) coupled between the second input/output bus (120) and the host bus (100) , the second bus bridge (105) being used for transferring information between the host bus (100) and the second input/output bus (120) , and a third input/output interface (121 , 122) , coupled to the second input/output bus (120) , which provides an interface between a third external input/output system and the second input/output bus (120) ;
   wherein the input/output processor (113) , is also coupled to the second input/output bus (120) , the input/output processor (113) controlling data transactions through the third input/output interface (121 , 122) , the local memory (125) providing temporary storage (data item) for data transactions through the third input/output interface (121 , 122) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (temporary storage) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0747829A1
CLAIM 4 A computer system as in one of claims 1 to 3 additionally comprising : a second input/output bus (120) ;
a second bus bridge (105) coupled between the second input/output bus (120) and the host bus (100) , the second bus bridge (105) being used for transferring information between the host bus (100) and the second input/output bus (120) , and a third input/output interface (121 , 122) , coupled to the second input/output bus (120) , which provides an interface between a third external input/output system and the second input/output bus (120) ;
   wherein the input/output processor (113) , is also coupled to the second input/output bus (120) , the input/output processor (113) controlling data transactions through the third input/output interface (121 , 122) , the local memory (125) providing temporary storage (data item) for data transactions through the third input/output interface (121 , 122) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (temporary storage) to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (transferring data) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		EP0747829A1
CLAIM 4 A computer system as in one of claims 1 to 3 additionally comprising : a second input/output bus (120) ;
a second bus bridge (105) coupled between the second input/output bus (120) and the host bus (100) , the second bus bridge (105) being used for transferring information between the host bus (100) and the second input/output bus (120) , and a third input/output interface (121 , 122) , coupled to the second input/output bus (120) , which provides an interface between a third external input/output system and the second input/output bus (120) ;
   wherein the input/output processor (113) , is also coupled to the second input/output bus (120) , the input/output processor (113) controlling data transactions through the third input/output interface (121 , 122) , the local memory (125) providing temporary storage (data item) for data transactions through the third input/output interface (121 , 122) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the third set contains valid data . 		EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (temporary storage) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		EP0747829A1
CLAIM 4 A computer system as in one of claims 1 to 3 additionally comprising : a second input/output bus (120) ;
a second bus bridge (105) coupled between the second input/output bus (120) and the host bus (100) , the second bus bridge (105) being used for transferring information between the host bus (100) and the second input/output bus (120) , and a third input/output interface (121 , 122) , coupled to the second input/output bus (120) , which provides an interface between a third external input/output system and the second input/output bus (120) ;
   wherein the input/output processor (113) , is also coupled to the second input/output bus (120) , the input/output processor (113) controlling data transactions through the third input/output interface (121 , 122) , the local memory (125) providing temporary storage (data item) for data transactions through the third input/output interface (121 , 122) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (temporary storage) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		EP0747829A1
CLAIM 4 A computer system as in one of claims 1 to 3 additionally comprising : a second input/output bus (120) ;
a second bus bridge (105) coupled between the second input/output bus (120) and the host bus (100) , the second bus bridge (105) being used for transferring information between the host bus (100) and the second input/output bus (120) , and a third input/output interface (121 , 122) , coupled to the second input/output bus (120) , which provides an interface between a third external input/output system and the second input/output bus (120) ;
   wherein the input/output processor (113) , is also coupled to the second input/output bus (120) , the input/output processor (113) controlling data transactions through the third input/output interface (121 , 122) , the local memory (125) providing temporary storage (data item) for data transactions through the third input/output interface (121 , 122) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (temporary storage) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		EP0747829A1
CLAIM 4 A computer system as in one of claims 1 to 3 additionally comprising : a second input/output bus (120) ;
a second bus bridge (105) coupled between the second input/output bus (120) and the host bus (100) , the second bus bridge (105) being used for transferring information between the host bus (100) and the second input/output bus (120) , and a third input/output interface (121 , 122) , coupled to the second input/output bus (120) , which provides an interface between a third external input/output system and the second input/output bus (120) ;
   wherein the input/output processor (113) , is also coupled to the second input/output bus (120) , the input/output processor (113) controlling data transactions through the third input/output interface (121 , 122) , the local memory (125) providing temporary storage (data item) for data transactions through the third input/output interface (121 , 122) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .

US6618736B1
CLAIM 53 . An computer program product (first input) for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (temporary storage) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		EP0747829A1
CLAIM 2 A computing system as in claim 1 wherein a first data transfer between the first input (computer program product) /output interface (41 ;
111) and the second input/output interface (42 ;
112) is set up by control information transferred between the host procesor (31 , 32 ;
101 , 102) and the embedded processor (44 ;
124) .

EP0747829A1
CLAIM 4 A computer system as in one of claims 1 to 3 additionally comprising : a second input/output bus (120) ;
a second bus bridge (105) coupled between the second input/output bus (120) and the host bus (100) , the second bus bridge (105) being used for transferring information between the host bus (100) and the second input/output bus (120) , and a third input/output interface (121 , 122) , coupled to the second input/output bus (120) , which provides an interface between a third external input/output system and the second input/output bus (120) ;
   wherein the input/output processor (113) , is also coupled to the second input/output bus (120) , the input/output processor (113) controlling data transactions through the third input/output interface (121 , 122) , the local memory (125) providing temporary storage (data item) for data transactions through the third input/output interface (121 , 122) .

EP0747829A1
CLAIM 8 A method for controlling data transfers over an input/output bus (40 ;
110) in a computing system , comprising the steps of : (a) setting up all data transfers to be performed over the input/output bus (40 ;
110) using an input/output processor (43 ;
113) so that data transfers between one of a plurality of input/output interfaces (41 , 42 ;
111 , 112) , connected to the input/output bus (40 ;
110) , and a local memory (45 ;
125) witin the input/output processor (43 ;
113) is set up by control information sent between the input/output processor (43 ;
113) and a host processor (31 , 32 ;
101 , 102) connected to a host bus (30 ;
100) , the control information passing through a bus bridge (34 ;
104) connected between the input/output bus (40 ;
110) and the host bus (30 ;
100) ;
and , (b) during each data transfer set up in step (a) , transferring data (remote storage device, corresponding storage unit) over the input/output bus (40 ;
110) between one of the plurality of input/output interfaces (41 , 42 ;
111 , 112) and the local memory (45 ;
125) within the input/output processor (43 ;
113) .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5778419A

Filed: 1996-02-23     Issued: 1998-07-07

DRAM with high bandwidth interface that uses packets and arbitration

(Original Assignee) Microunity Systems Engineering Inc     (Current Assignee) Microunity Systems Engineering Inc

Craig C. Hansen, Timothy B. Robinson, Alan G. Corry
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit (stores data) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (stores data) of the second set contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (stores data) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (stores data) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

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CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (stores data) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (stores data) of the third set contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (stores data) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (stores data) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (stores data) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (stores data) of the second set for which an indication of valid data is stored in the first usage map . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (stores data) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (stores data) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (stores data) contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (stores data) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (stores data) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (stores data) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (stores data) of the second set contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (stores data) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (stores data) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (stores data) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (stores data) of the first set for which an indication of valid data is stored in the first usage map . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (stores data) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (stores data) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (stores data) of the second set contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (stores data) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (stores data) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (stores data) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (stores data) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (stores data) of the third set contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (stores data) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (stores data) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (stores data) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (stores data) of the second set for which an indication of valid data is stored in the first usage map . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (stores data) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (stores data) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code (data word) for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5778419A
CLAIM 1 . A memory chip , comprising : a memory array that decodes , arbitrates between , and executes memory array access commands , and for generates memory array access responses ;
and a high bandwidth data interface , coupled with the memory array , comprising ;
a data path , an interface controller , and a packet buffer , said data path is coupled with the packet buffer and interface controller , and receives an input data stream through an input port and transmits an output data stream through an output port , said interface controller is coupled with the packet buffer , and controls flow of the input and output data streams within the memory chip , and said packet buffer is coupled between the data path and the memory array , and temporarily stores data (storage unit, storage unit reading module) from the input and output data streams , and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array .

US5778419A
CLAIM 45 . The method for processing a stream of data of claim 44 , wherein the plurality of fixed bit length data fields of each of certain input packets further comprises a write data word (program code) .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5751997A

Filed: 1996-01-19     Issued: 1998-05-12

Method and apparatus for transferring archival data among an arbitrarily large number of computer devices in a networked computer environment

(Original Assignee) Apple Computer Inc     (Current Assignee) Apple Inc

Steven E. Kullick, Charles S. Spirakis, Diane J. Titus
US6618736B1
CLAIM 1 . A method for file system (external storage, first backup, data files) creation and archival comprising : providing a first set of storage units (one disk, minimum time) and a second set (including one) of storage units , each storage unit (one disk, minimum time) of the first set corresponding to a storage unit of the second set ;

providing a first usage (time t) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (one disk, minimum time) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US5751997A
CLAIM 15 . In a networked computer system having a communication network interconnecting one or more primary storage devices , one or more secondary storage devices and a plurality of computer devices , each computer device having one or more storage resources , a method for transferring data from one or more of the storage resources , said method comprising the steps of : initiating and controlling two or more concurrent processes by each active primary storage device , wherein each process initiates a connection between a computer device and a secondary storage device ;
indicating when a transfer of data from the primary storage device to the secondary storage device should occur ;
transferring data from the primary storage device to the secondary storage device in response to such indicating ;
forming for a storage resource of a computer device a new index and a corresponding data file on a secondary storage device by comparing and merging data from a primary storage device index and data files (file system, file systems) with previously-existing index and data file corresponding to the storage resource , said previously-existing index and data file being stored on the secondary storage device ;
checking whether the primary storage device has an index that defines the data from the storage resource ;
if the primary storage device does not have the index , checking to see if the secondary storage device has such an index ;
if the secondary storage device has a version of the index , sending a copy of the secondary storage device version of the index to the computer device via the primary storage device , if the secondary storage device does not have such an index , copying data and corresponding information from the storage resource of the computer device to the secondary storage device , storing the data in a data file on the secondary storage device or external storage (file system, file systems) devices connected to the secondary storage device , creating an index for accessing the data in the backup data file , and storing a copy of the index from the computer device on the secondary storage device ;
determining which data on the storage resource to update ;
creating an index entry for the determined data ;
sending index entries and a copy of the determined data to the primary storage device ;
and forming a new index and a new corresponding data file on the primary storage device by comparing and merging newly-acquired determined data from the computer device contained in the most recent index and data files with the previously existing index and data files already stored on the primary storage device .

US5751997A
CLAIM 16 . In a networked computer system having a communication network interconnecting a plurality of devices , the devices including one (second set) or more primary storage devices , one or more secondary storage devices and a plurality of computer devices , each computer device having one or more storage resources , a method for transferring among the devices data from the storage resources , said plurality of devices capable of creating a plurality of parallel processes , said method comprising the steps of : assigning a secondary storage device to a storage resource ;
performing a backup initialization operation for the storage resource from which data is being transferred , the backup initialization operation forming a first full index and a first backup (file system, file systems) data file for each storage resource being stored on a secondary storage device ;
repeatedly performing backup cycles for the storage resource from which data is being transferred , during each backup cycle , determining from which files and directories on the storage resource data should be transferred ;
transferring from the computer device of the storage resource a second full index for the storage resource , the second full index having an entry for each file and directory on the storage resource , and a second backup data file for the storage resource , the second backup data file including data for the determined storage resource' ;
s files and directories , and storing the second full index and the second backup data file on the primary storage device , incorporating the second full index and the second backup data file with a previously-stored second full index and a previously-stored second backup data file , if any exist , on the primary storage device , the backup cycles being repeatedly performed until a transfer of data from the primary storage device is indicated ;
indicating when a transfer of data from the primary storage device to a secondary storage device should occur ;
transferring data from the primary storage device to the secondary storage device in response to such indicating , the data comprising with respect to a particular storage resource , the second full index and the second backup data file stored on the primary storage device ;
incorporating the data transferred from the primary storage device into the first full index and the first backup data file stored on the secondary storage device to produce a new first full index having an index entry for each file and directory on the storage resource and a new first backup data file having data for each file and directory , the data for a particular index entry being from the second backup data file if the second backup data file contains data for that particular index entry and being from the first backup data file if the second backup data file does not contain data for that particular index entry ;
and storing the new first full index and the new first backup data file on the secondary storage device .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets (time interval) of storage units (one disk, minimum time) are stored in a same storage device . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US5751997A
CLAIM 19 . The method of claim 16 wherein the step of indicating a transfer from the primary storage device to the secondary storage device occurs at specified time interval (second sets) s .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (one disk, minimum time) is stored in a local storage device and the second set (including one) of storage units is stored in a remote storage device (transferring data) . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US5751997A
CLAIM 15 . In a networked computer system having a communication network interconnecting one or more primary storage devices , one or more secondary storage devices and a plurality of computer devices , each computer device having one or more storage resources , a method for transferring data (remote storage device) from one or more of the storage resources , said method comprising the steps of : initiating and controlling two or more concurrent processes by each active primary storage device , wherein each process initiates a connection between a computer device and a secondary storage device ;
indicating when a transfer of data from the primary storage device to the secondary storage device should occur ;
transferring data from the primary storage device to the secondary storage device in response to such indicating ;
forming for a storage resource of a computer device a new index and a corresponding data file on a secondary storage device by comparing and merging data from a primary storage device index and data files with previously-existing index and data file corresponding to the storage resource , said previously-existing index and data file being stored on the secondary storage device ;
checking whether the primary storage device has an index that defines the data from the storage resource ;
if the primary storage device does not have the index , checking to see if the secondary storage device has such an index ;
if the secondary storage device has a version of the index , sending a copy of the secondary storage device version of the index to the computer device via the primary storage device , if the secondary storage device does not have such an index , copying data and corresponding information from the storage resource of the computer device to the secondary storage device , storing the data in a data file on the secondary storage device or external storage devices connected to the secondary storage device , creating an index for accessing the data in the backup data file , and storing a copy of the index from the computer device on the secondary storage device ;
determining which data on the storage resource to update ;
creating an index entry for the determined data ;
sending index entries and a copy of the determined data to the primary storage device ;
and forming a new index and a new corresponding data file on the primary storage device by comparing and merging newly-acquired determined data from the computer device contained in the most recent index and data files with the previously existing index and data files already stored on the primary storage device .

US5751997A
CLAIM 16 . In a networked computer system having a communication network interconnecting a plurality of devices , the devices including one (second set) or more primary storage devices , one or more secondary storage devices and a plurality of computer devices , each computer device having one or more storage resources , a method for transferring among the devices data from the storage resources , said plurality of devices capable of creating a plurality of parallel processes , said method comprising the steps of : assigning a secondary storage device to a storage resource ;
performing a backup initialization operation for the storage resource from which data is being transferred , the backup initialization operation forming a first full index and a first backup data file for each storage resource being stored on a secondary storage device ;
repeatedly performing backup cycles for the storage resource from which data is being transferred , during each backup cycle , determining from which files and directories on the storage resource data should be transferred ;
transferring from the computer device of the storage resource a second full index for the storage resource , the second full index having an entry for each file and directory on the storage resource , and a second backup data file for the storage resource , the second backup data file including data for the determined storage resource' ;
s files and directories , and storing the second full index and the second backup data file on the primary storage device , incorporating the second full index and the second backup data file with a previously-stored second full index and a previously-stored second backup data file , if any exist , on the primary storage device , the backup cycles being repeatedly performed until a transfer of data from the primary storage device is indicated ;
indicating when a transfer of data from the primary storage device to a secondary storage device should occur ;
transferring data from the primary storage device to the secondary storage device in response to such indicating , the data comprising with respect to a particular storage resource , the second full index and the second backup data file stored on the primary storage device ;
incorporating the data transferred from the primary storage device into the first full index and the first backup data file stored on the secondary storage device to produce a new first full index having an index entry for each file and directory on the storage resource and a new first backup data file having data for each file and directory , the data for a particular index entry being from the second backup data file if the second backup data file contains data for that particular index entry and being from the first backup data file if the second backup data file does not contain data for that particular index entry ;
and storing the new first full index and the new first backup data file on the secondary storage device .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one disk, minimum time) (one disk, minimum time) of the second set (including one) contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the storage units (one disk, minimum time) of the second set (including one) contain valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk, minimum time) of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit (one disk, minimum time) of the second set (including one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk, minimum time) of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit (one disk, minimum time) of the second set (including one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (one disk, minimum time) , each storage unit (one disk, minimum time) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (one disk, minimum time) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one disk, minimum time) (one disk, minimum time) of the third set contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (one disk, minimum time) of the third set contain valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk, minimum time) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (one disk, minimum time) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk, minimum time) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (one disk, minimum time) of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set (including one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (one disk, minimum time) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (one disk, minimum time) of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set (including one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (one disk, minimum time) of the second set (including one) for which an indication of valid data is stored in the first usage (time t) map . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (including one) of storage units (one disk, minimum time) with the third set of storage units . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (one disk, minimum time) of the second set (including one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (one disk, minimum time) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (external storage, first backup, data files) of a plurality of servers , the method comprising : providing a set of shared storage units (one disk, minimum time) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (one disk, minimum time) ;

and providing a first usage (time t) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (external storage, first backup, data files) of each server comprises a combination of the set of shared storage units (one disk, minimum time) and the first set of private storage units for the server . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (one disk, minimum time) and the first usage (time t) map of a first server . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (one disk, minimum time) are stored in a same storage device . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (one disk, minimum time) are stored a local storage device and the private storage units are stored in a remote storage device (transferring data) . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (one disk, minimum time) contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the private storage units (one disk, minimum time) contain valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk, minimum time) ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk, minimum time) ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (including one) of private storage units (one disk, minimum time) , each private storage unit (one disk, minimum time) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (one disk, minimum time) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (one disk, minimum time) of the second set (including one) contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (one disk, minimum time) of the second set (including one) contain valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk, minimum time) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (including one) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk, minimum time) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (including one) does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one disk, minimum time) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (including one) does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (one disk, minimum time) of the first set for which an indication of valid data is stored in the first usage (time t) map . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (one disk, minimum time) with the second set (including one) of private storage units . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (one disk, minimum time) of the first set that contain valid data to those corresponding private storage units of the second set (including one) that do not contain valid data ;

and for each private storage unit (one disk, minimum time) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (external storage, first backup, data files) within at least one storage device comprising a first set of storage units (one disk, minimum time) and a second set (including one) of storage units , each storage unit (one disk, minimum time) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (one disk, minimum time) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets (time interval) of storage units (one disk, minimum time) are stored in a same storage device . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US5751997A
CLAIM 19 . The method of claim 16 wherein the step of indicating a transfer from the primary storage device to the secondary storage device occurs at specified time interval (second sets) s .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (one disk, minimum time) is stored in a local storage device and the second set (including one) of storage units is stored in a remote storage device (transferring data) . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one disk, minimum time) (one disk, minimum time) of the second set (including one) contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (time t) map is initially reset to indicate that none of the storage units (one disk, minimum time) of the second set (including one) contain valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk, minimum time) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit (one disk, minimum time) of the second set (including one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk, minimum time) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit (one disk, minimum time) of the second set (including one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (one disk, minimum time) , each storage unit (one disk, minimum time) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (one disk, minimum time) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (one disk, minimum time) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one disk, minimum time) (one disk, minimum time) of the third set contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (one disk, minimum time) of the third set contain valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk, minimum time) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (one disk, minimum time) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk, minimum time) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (one disk, minimum time) of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set (including one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one disk, minimum time) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (one disk, minimum time) of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set (including one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (one disk, minimum time) of the second set (including one) for which an indication of valid data is stored in the first usage (time t) map . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (including one) of storage units (one disk, minimum time) with the third set of storage units . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (one disk, minimum time) of the second set (including one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (one disk, minimum time) update module (one disk, minimum time) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (external storage, first backup, data files) within at least one storage device comprising a first set of storage units (one disk, minimum time) and a second set (including one) of storage units , each storage unit (one disk, minimum time) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (one disk, minimum time) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5751997A
CLAIM 5 . The method as defined in claim 1 further comprising the steps of : setting a minimum time (corresponding storage unit, storage unit update module, storage units, storage unit, corresponding storage units) between backups for a disk on a computer device ;
recording when a computer device sends index entries and data for a disk to a primary storage device ;
accessing a current date and time ;
checking at each attempt to perform a transfer of data for a disk whether the minimum time between backups for a disk elapsed since the computer device last sent index entries and data for a disk to a primary storage device ;
and performing the attempted data transfer only if the minimum time has elapsed .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5765173A

Filed: 1996-01-11     Issued: 1998-06-09

High performance backup via selective file saving which can perform incremental backups and exclude files and uses a changed block signature list

(Original Assignee) Connected Corp     (Current Assignee) Autonomy Inc

David Cane, David Hirschman
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units (data areas) and a second set of storage units , each storage unit (one file) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (data areas) are stored in a same storage device . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (data areas) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one file) of the second set contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (data areas) of the second set contain valid data . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (one file) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (one file) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (data areas) , each storage unit (one file) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one file) of the third set contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (data areas) of the third set contain valid data . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (one file) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (one file) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (one file) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (one file) of the second set for which an indication of valid data is stored in the first usage map . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units (data areas) with the third set of storage units . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (data areas) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (one file) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (data areas) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (one file) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units (data areas) and the first set of private storage units for the server . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (data areas) and the first usage map of a first server . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (data areas) are stored in a same storage device . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (data areas) are stored a local storage device and the private storage units are stored in a remote storage device . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (one file) contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (data areas) contain valid data . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one file) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one file) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units (data areas) , each private storage unit (one file) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (one file) of the second set contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (data areas) of the second set contain valid data . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one file) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one file) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (one file) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (one file) of the first set for which an indication of valid data is stored in the first usage map . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (data areas) with the second set of private storage units . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (data areas) of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (one file) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units (data areas) and a second set of storage units , each storage unit (one file) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (data areas) are stored in a same storage device . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (data areas) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one file) of the second set contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (data areas) of the second set contain valid data . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one file) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one file) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (data areas) , each storage unit (one file) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (one file) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (one file) of the third set contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (data areas) of the third set contain valid data . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one file) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one file) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (one file) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (one file) of the second set for which an indication of valid data is stored in the first usage map . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units (data areas) with the third set of storage units . 		US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (data areas) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (one file) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units (data areas) and a second set of storage units , each storage unit (one file) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5765173A
CLAIM 10 . The method of claim 9 wherein said scanning for files with similar modification dates includes considering only groups of files wherein at least one file (storage unit, corresponding storage unit) in the group contains computer instructions .

US5765173A
CLAIM 11 . The method of claim 1 including recognizing files which contain computer instructions , and which have differing patches , wherein a patch distinguishes instantiations of similar applications by comprising non-instruction data areas (storage units, corresponding storage units) and excluding such files from backup .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		JPH09185465A

Filed: 1995-12-27     Issued: 1997-07-15

ライブラリ装置、及び、情報処理システム、及び、制御モジュール

(Original Assignee) Fujitsu Ltd; 富士通株式会社     

Kazuhiko Inoue, Satoshi Kubota, 聡 久保田, 和彦 井上
US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (ユニット) . 		JPH09185465A
CLAIM 1 【請求項１】 記録媒体をドライブするドライバと、該 記録媒体を格納する記録媒体格納部と、該ドライバと該 記録媒体格納部との間で該記録媒体を搬送する搬送機構 とを有するライブラリ装置において、 前記記録媒体毎に論理ユニット (remote storage device) 番号を設定し、該論理ユ ニット番号により前記記録媒体を管理することを特徴と するライブラリ装置。
US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (ユニット) . 		JPH09185465A
CLAIM 1 【請求項１】 記録媒体をドライブするドライバと、該 記録媒体を格納する記録媒体格納部と、該ドライバと該 記録媒体格納部との間で該記録媒体を搬送する搬送機構 とを有するライブラリ装置において、 前記記録媒体毎に論理ユニット (remote storage device) 番号を設定し、該論理ユ ニット番号により前記記録媒体を管理することを特徴と するライブラリ装置。
US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module (制御モジュール) for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (制御モジュール) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module (制御モジュール) for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH09185465A
CLAIM 8 【請求項８】 記録媒体を格納棚とドライバとの間で移 動して情報を記録／再生するライブラリ装置とＳＣＳＩ バスとの間に設けられ、 前記ＳＣＳＩバスを介して指示される論理ユニット番号 に応じて前記ライブラリ装置を制御し、 前記ライブラリ装置に格納された前記記録媒体の内一つ の記録媒体を選択して記録／再生させることを特徴とす る制御モジュール (archival module, interception module, storage unit writing module, usage map updating module, storage unit reading module, merging module, storage unit update module) 。
US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (ユニット) . 		JPH09185465A
CLAIM 1 【請求項１】 記録媒体をドライブするドライバと、該 記録媒体を格納する記録媒体格納部と、該ドライバと該 記録媒体格納部との間で該記録媒体を搬送する搬送機構 とを有するライブラリ装置において、 前記記録媒体毎に論理ユニット (remote storage device) 番号を設定し、該論理ユ ニット番号により前記記録媒体を管理することを特徴と するライブラリ装置。
US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module (制御モジュール) is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (制御モジュール) configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		JPH09185465A
CLAIM 8 【請求項８】 記録媒体を格納棚とドライバとの間で移 動して情報を記録／再生するライブラリ装置とＳＣＳＩ バスとの間に設けられ、 前記ＳＣＳＩバスを介して指示される論理ユニット番号 に応じて前記ライブラリ装置を制御し、 前記ライブラリ装置に格納された前記記録媒体の内一つ の記録媒体を選択して記録／再生させることを特徴とす る制御モジュール (archival module, interception module, storage unit writing module, usage map updating module, storage unit reading module, merging module, storage unit update module) 。
US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module (制御モジュール) is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (制御モジュール) configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		JPH09185465A
CLAIM 8 【請求項８】 記録媒体を格納棚とドライバとの間で移 動して情報を記録／再生するライブラリ装置とＳＣＳＩ バスとの間に設けられ、 前記ＳＣＳＩバスを介して指示される論理ユニット番号 に応じて前記ライブラリ装置を制御し、 前記ライブラリ装置に格納された前記記録媒体の内一つ の記録媒体を選択して記録／再生させることを特徴とす る制御モジュール (archival module, interception module, storage unit writing module, usage map updating module, storage unit reading module, merging module, storage unit update module) 。
US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module (制御モジュール) is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module (制御モジュール) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module (制御モジュール) is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JPH09185465A
CLAIM 8 【請求項８】 記録媒体を格納棚とドライバとの間で移 動して情報を記録／再生するライブラリ装置とＳＣＳＩ バスとの間に設けられ、 前記ＳＣＳＩバスを介して指示される論理ユニット番号 に応じて前記ライブラリ装置を制御し、 前記ライブラリ装置に格納された前記記録媒体の内一つ の記録媒体を選択して記録／再生させることを特徴とす る制御モジュール (archival module, interception module, storage unit writing module, usage map updating module, storage unit reading module, merging module, storage unit update module) 。
US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module (制御モジュール) is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (制御モジュール) configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		JPH09185465A
CLAIM 8 【請求項８】 記録媒体を格納棚とドライバとの間で移 動して情報を記録／再生するライブラリ装置とＳＣＳＩ バスとの間に設けられ、 前記ＳＣＳＩバスを介して指示される論理ユニット番号 に応じて前記ライブラリ装置を制御し、 前記ライブラリ装置に格納された前記記録媒体の内一つ の記録媒体を選択して記録／再生させることを特徴とす る制御モジュール (archival module, interception module, storage unit writing module, usage map updating module, storage unit reading module, merging module, storage unit update module) 。
US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module (制御モジュール) is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (制御モジュール) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		JPH09185465A
CLAIM 8 【請求項８】 記録媒体を格納棚とドライバとの間で移 動して情報を記録／再生するライブラリ装置とＳＣＳＩ バスとの間に設けられ、 前記ＳＣＳＩバスを介して指示される論理ユニット番号 に応じて前記ライブラリ装置を制御し、 前記ライブラリ装置に格納された前記記録媒体の内一つ の記録媒体を選択して記録／再生させることを特徴とす る制御モジュール (archival module, interception module, storage unit writing module, usage map updating module, storage unit reading module, merging module, storage unit update module) 。
US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module (制御モジュール) is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (制御モジュール) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		JPH09185465A
CLAIM 8 【請求項８】 記録媒体を格納棚とドライバとの間で移 動して情報を記録／再生するライブラリ装置とＳＣＳＩ バスとの間に設けられ、 前記ＳＣＳＩバスを介して指示される論理ユニット番号 に応じて前記ライブラリ装置を制御し、 前記ライブラリ装置に格納された前記記録媒体の内一つ の記録媒体を選択して記録／再生させることを特徴とす る制御モジュール (archival module, interception module, storage unit writing module, usage map updating module, storage unit reading module, merging module, storage unit update module) 。
US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module (制御モジュール) configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage map . 		JPH09185465A
CLAIM 8 【請求項８】 記録媒体を格納棚とドライバとの間で移 動して情報を記録／再生するライブラリ装置とＳＣＳＩ バスとの間に設けられ、 前記ＳＣＳＩバスを介して指示される論理ユニット番号 に応じて前記ライブラリ装置を制御し、 前記ライブラリ装置に格納された前記記録媒体の内一つ の記録媒体を選択して記録／再生させることを特徴とす る制御モジュール (archival module, interception module, storage unit writing module, usage map updating module, storage unit reading module, merging module, storage unit update module) 。
US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module (制御モジュール) configured to merge the second set of storage units with the third set of storage units . 		JPH09185465A
CLAIM 8 【請求項８】 記録媒体を格納棚とドライバとの間で移 動して情報を記録／再生するライブラリ装置とＳＣＳＩ バスとの間に設けられ、 前記ＳＣＳＩバスを介して指示される論理ユニット番号 に応じて前記ライブラリ装置を制御し、 前記ライブラリ装置に格納された前記記録媒体の内一つ の記録媒体を選択して記録／再生させることを特徴とす る制御モジュール (archival module, interception module, storage unit writing module, usage map updating module, storage unit reading module, merging module, storage unit update module) 。
US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module (制御モジュール) is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (制御モジュール) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		JPH09185465A
CLAIM 8 【請求項８】 記録媒体を格納棚とドライバとの間で移 動して情報を記録／再生するライブラリ装置とＳＣＳＩ バスとの間に設けられ、 前記ＳＣＳＩバスを介して指示される論理ユニット番号 に応じて前記ライブラリ装置を制御し、 前記ライブラリ装置に格納された前記記録媒体の内一つ の記録媒体を選択して記録／再生させることを特徴とす る制御モジュール (archival module, interception module, storage unit writing module, usage map updating module, storage unit reading module, merging module, storage unit update module) 。



US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5729743A

Filed: 1995-11-30     Issued: 1998-03-17

Computer apparatus and method for merging system deltas

(Original Assignee) DeltaTech Res Inc     (Current Assignee) DOUBLE-TAKE SOFTWARE CANADA Inc ; DeltaTech Res Inc

Mark Squibb
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (time t) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage (time t) map . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (time t) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage (time t) map of a first server . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set for which an indication of valid data is stored in the first usage (time t) map . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (time t) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage (time t) map . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US6618736B1
CLAIM 53 . An computer program product (recorded data) for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5729743A
CLAIM 10 . A method as in claim 9 , wherein the step of processing any clones of an element , immediately after processing the cloned element , comprises the steps of : a) replaying the data of the cloned element once for each of its clones ;
b) processing a next clone each time t (first usage) he data of the cloned element is replayed .

US5729743A
CLAIM 12 . A method as in claim 10 , wherein the step of replaying the data of the cloned element comprises the steps of : a) recording the data of each cloned element during its processing through the system filter ;
and c) replaying the recorded data (computer program product) each time the data of the cloned element is required to be replayed by claim 10 .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5778395A

Filed: 1995-10-23     Issued: 1998-07-07

System for backing up files from disk volumes on multiple nodes of a computer network

(Original Assignee) STAC Inc     (Current Assignee) Veritas Technologies LLC

Douglas L. Whiting, Tom Dilatush
US6618736B1
CLAIM 1 . A method for file system (file system, data files) creation and archival comprising : providing a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (function value) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5778395A
CLAIM 1 . A method for backing up data files (file system, file systems) stored on a disk volume of a node of a computer network to a backup storage means , said backup storage means containing data files already backed up from other nodes on said computer network , said method comprising the steps of : searching through a list of said files already backed up from said other nodes onto said backup storage means for a match to files to be backed up from said disk volume ;
operative when no match is found between a file to be backed up from said disk volume and any of said files already contained in said list , storing on said backup storage means a complete representation of the contents of said file to be backed up , computing an index that indicates the location on said backup storage means of said complete representation , and adding to said list an entry describing said file to be backed up from said disk volume ;
operative when a match is found between a file to be backed up from said disk volume and a file already contained in said list , computing an index that indicates the location on said backup storage means of a complete representation of the contents of said file already contained in said list , said index capable of indicating files previously backed up from said other nodes ;
storing a data structure specifying a portion of the directory structure of said disk volume at the time of the backup operation , said data structure including , for each said file backed up from said disk volume , said index indicating the location of said complete representation , either of said file to be backed up or of said file already contained in said list , depending on the outcome of said search through said list ;
and so that a file on another node that is duplicated on said disk volume may be identified so that only one copy of the contents of said file is stored on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 15 . The method of any of claims 1-8 in which the contents of a particular backup operation are mounted as a restored disk volume having a directory structure identical to that of the original disk volume at the time of said backup operation , whereby said files on said restored disk volume may be accessed from a software application that uses normal file system (file system, file systems) input/output calls .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (following steps) are stored in a same storage device . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (following steps) is stored in a local storage device and the second set (following steps) of storage units is stored in a remote storage device . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (function value) of the second set (following steps) contains valid data . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (following steps) of the second set (following steps) contain valid data . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (function value) of the second set (following steps) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (function value) of the second set (following steps) does not contain valid data , reading the data item from the storage unit of the first set . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (compression algorithm) of storage units (following steps) , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (function value) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (function value) of the third set (compression algorithm) contains valid data . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (following steps) of the third set (compression algorithm) contain valid data . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (function value) of the third set (compression algorithm) contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (function value) of the third set (compression algorithm) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (function value) of the third set (compression algorithm) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , reading the data item from the storage unit of the first set . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (following steps) for which an indication of valid data is stored in the first usage map . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (following steps) of storage units (following steps) with the third set (compression algorithm) of storage units . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (following steps) of the second set (following steps) that contain valid data to those corresponding storage units of the third set (compression algorithm) that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (file system, data files) of a plurality of servers , the method comprising : providing a set of shared storage units (following steps) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5778395A
CLAIM 1 . A method for backing up data files (file system, file systems) stored on a disk volume of a node of a computer network to a backup storage means , said backup storage means containing data files already backed up from other nodes on said computer network , said method comprising the steps of : searching through a list of said files already backed up from said other nodes onto said backup storage means for a match to files to be backed up from said disk volume ;
operative when no match is found between a file to be backed up from said disk volume and any of said files already contained in said list , storing on said backup storage means a complete representation of the contents of said file to be backed up , computing an index that indicates the location on said backup storage means of said complete representation , and adding to said list an entry describing said file to be backed up from said disk volume ;
operative when a match is found between a file to be backed up from said disk volume and a file already contained in said list , computing an index that indicates the location on said backup storage means of a complete representation of the contents of said file already contained in said list , said index capable of indicating files previously backed up from said other nodes ;
storing a data structure specifying a portion of the directory structure of said disk volume at the time of the backup operation , said data structure including , for each said file backed up from said disk volume , said index indicating the location of said complete representation , either of said file to be backed up or of said file already contained in said list , depending on the outcome of said search through said list ;
and so that a file on another node that is duplicated on said disk volume may be identified so that only one copy of the contents of said file is stored on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 15 . The method of any of claims 1-8 in which the contents of a particular backup operation are mounted as a restored disk volume having a directory structure identical to that of the original disk volume at the time of said backup operation , whereby said files on said restored disk volume may be accessed from a software application that uses normal file system (file system, file systems) input/output calls .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (file system, data files) of each server comprises a combination of the set of shared storage units (following steps) and the first set of private storage units for the server . 		US5778395A
CLAIM 1 . A method for backing up data files (file system, file systems) stored on a disk volume of a node of a computer network to a backup storage means , said backup storage means containing data files already backed up from other nodes on said computer network , said method comprising the steps of : searching through a list of said files already backed up from said other nodes onto said backup storage means for a match to files to be backed up from said disk volume ;
operative when no match is found between a file to be backed up from said disk volume and any of said files already contained in said list , storing on said backup storage means a complete representation of the contents of said file to be backed up , computing an index that indicates the location on said backup storage means of said complete representation , and adding to said list an entry describing said file to be backed up from said disk volume ;
operative when a match is found between a file to be backed up from said disk volume and a file already contained in said list , computing an index that indicates the location on said backup storage means of a complete representation of the contents of said file already contained in said list , said index capable of indicating files previously backed up from said other nodes ;
storing a data structure specifying a portion of the directory structure of said disk volume at the time of the backup operation , said data structure including , for each said file backed up from said disk volume , said index indicating the location of said complete representation , either of said file to be backed up or of said file already contained in said list , depending on the outcome of said search through said list ;
and so that a file on another node that is duplicated on said disk volume may be identified so that only one copy of the contents of said file is stored on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 15 . The method of any of claims 1-8 in which the contents of a particular backup operation are mounted as a restored disk volume having a directory structure identical to that of the original disk volume at the time of said backup operation , whereby said files on said restored disk volume may be accessed from a software application that uses normal file system (file system, file systems) input/output calls .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (following steps) and the first usage map of a first server . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (file system, data files) for a second server using the stored template . 		US5778395A
CLAIM 1 . A method for backing up data files (file system, file systems) stored on a disk volume of a node of a computer network to a backup storage means , said backup storage means containing data files already backed up from other nodes on said computer network , said method comprising the steps of : searching through a list of said files already backed up from said other nodes onto said backup storage means for a match to files to be backed up from said disk volume ;
operative when no match is found between a file to be backed up from said disk volume and any of said files already contained in said list , storing on said backup storage means a complete representation of the contents of said file to be backed up , computing an index that indicates the location on said backup storage means of said complete representation , and adding to said list an entry describing said file to be backed up from said disk volume ;
operative when a match is found between a file to be backed up from said disk volume and a file already contained in said list , computing an index that indicates the location on said backup storage means of a complete representation of the contents of said file already contained in said list , said index capable of indicating files previously backed up from said other nodes ;
storing a data structure specifying a portion of the directory structure of said disk volume at the time of the backup operation , said data structure including , for each said file backed up from said disk volume , said index indicating the location of said complete representation , either of said file to be backed up or of said file already contained in said list , depending on the outcome of said search through said list ;
and so that a file on another node that is duplicated on said disk volume may be identified so that only one copy of the contents of said file is stored on said backup storage means .

US5778395A
CLAIM 15 . The method of any of claims 1-8 in which the contents of a particular backup operation are mounted as a restored disk volume having a directory structure identical to that of the original disk volume at the time of said backup operation , whereby said files on said restored disk volume may be accessed from a software application that uses normal file system (file system, file systems) input/output calls .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (following steps) are stored in a same storage device . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (following steps) are stored a local storage device and the private storage units are stored in a remote storage device . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (following steps) contain valid data . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (following steps) of private storage units (following steps) , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (function value) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (following steps) contains valid data . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (following steps) of the second set (following steps) contain valid data . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (following steps) with the second set (following steps) of private storage units . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (following steps) of the first set that contain valid data to those corresponding private storage units of the second set (following steps) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (file system, data files) within at least one storage device comprising a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (function value) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5778395A
CLAIM 1 . A method for backing up data files (file system, file systems) stored on a disk volume of a node of a computer network to a backup storage means , said backup storage means containing data files already backed up from other nodes on said computer network , said method comprising the steps of : searching through a list of said files already backed up from said other nodes onto said backup storage means for a match to files to be backed up from said disk volume ;
operative when no match is found between a file to be backed up from said disk volume and any of said files already contained in said list , storing on said backup storage means a complete representation of the contents of said file to be backed up , computing an index that indicates the location on said backup storage means of said complete representation , and adding to said list an entry describing said file to be backed up from said disk volume ;
operative when a match is found between a file to be backed up from said disk volume and a file already contained in said list , computing an index that indicates the location on said backup storage means of a complete representation of the contents of said file already contained in said list , said index capable of indicating files previously backed up from said other nodes ;
storing a data structure specifying a portion of the directory structure of said disk volume at the time of the backup operation , said data structure including , for each said file backed up from said disk volume , said index indicating the location of said complete representation , either of said file to be backed up or of said file already contained in said list , depending on the outcome of said search through said list ;
and so that a file on another node that is duplicated on said disk volume may be identified so that only one copy of the contents of said file is stored on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 15 . The method of any of claims 1-8 in which the contents of a particular backup operation are mounted as a restored disk volume having a directory structure identical to that of the original disk volume at the time of said backup operation , whereby said files on said restored disk volume may be accessed from a software application that uses normal file system (file system, file systems) input/output calls .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (following steps) are stored in a same storage device . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (following steps) is stored in a local storage device and the second set (following steps) of storage units is stored in a remote storage device . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (function value) of the second set (following steps) contains valid data . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (following steps) of the second set (following steps) contain valid data . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (function value) of the second set (following steps) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (function value) of the second set (following steps) does not contain valid data , to read the data item from the storage unit of the first set . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (compression algorithm) of storage units (following steps) , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (function value) of the third set (compression algorithm) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (function value) of the third set (compression algorithm) contains valid data . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (following steps) of the third set (compression algorithm) contain valid data . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (function value) of the third set (compression algorithm) contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (function value) of the third set (compression algorithm) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (function value) of the third set (compression algorithm) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , to read the data item from the storage unit of the first set . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (following steps) for which an indication of valid data is stored in the first usage map . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (following steps) of storage units (following steps) with the third set (compression algorithm) of storage units . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (following steps) of the second set (following steps) that contain valid data to those corresponding storage units of the third set (compression algorithm) that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5778395A
CLAIM 4 . The method of claim 3 in which the steps of storing said complete representation of the contents of said file to be backed up further includes the step of compressing portions of said representation using a lossless data compression algorithm (third set) before storing said representation on said backup storage means .

US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (file system, data files) within at least one storage device comprising a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (function value) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5778395A
CLAIM 12 . The method of claim 11 in which said search of said database includes the following steps (second set, storage units) : loading a first section of said database , said first section containing partial entries , each partial entry containing only a portion of an entry of said database ;
generating a new database entry of said file to be backed up ;
and searching through said first section for a match between said new database entry and said partial entries and , operative when a match is found between said new database entry and a partial entry of said first section , loading the remaining portions of said matching partial entry from the associated entry in a second section of said database , and comparing said new database entry with said remaining portion of said associated entry to determine whether there is a complete match between said new database entry and the complete database entry .

US5778395A
CLAIM 15 . The method of any of claims 1-8 in which the contents of a particular backup operation are mounted as a restored disk volume having a directory structure identical to that of the original disk volume at the time of said backup operation , whereby said files on said restored disk volume may be accessed from a software application that uses normal file system (file system, file systems) input/output calls .

US5778395A
CLAIM 18 . The method of any of claims 2-8 in which the differences between said file to be backed up and said previous version of said file are computed using a probabilistic algorithm , including the following steps : at the time when said previous version was backed up , storing on said backup storage means a set of hash function value (corresponding storage unit, corresponding storage units) s computed on fixed size chunks of said previous version ;
at the time of said backup , loading said previously stored hash function results ;
comparing said hash function results from said previous file version to hash function results computed on fixed size chunks of said file to be backed up ;
and operative when a chunk of said file to be backed up has the same hash value as a chunk of said previous file , representing said chunk of said file to be backed up by an index indicating said matching chunk of said previous version .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5748914A

Filed: 1995-10-19     Issued: 1998-05-05

Protocol for communication with dynamic memory

(Original Assignee) Rambus Inc     (Current Assignee) Rambus Inc

Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (more memory) of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (time t) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transmitting control information) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (following steps) are stored in a same storage device . 		US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (more memory) of storage units (following steps) is stored in a local storage device and the second set (following steps) of storage units is stored in a remote storage device (first location) . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location (remote storage device) of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time that is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transmitting control information) of the second set (following steps) contains valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the storage units (following steps) of the second set (following steps) contain valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (more memory) ;

and in response to the first usage (time t) map indicating that the corresponding storage unit (transmitting control information) of the second set (following steps) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (more memory) ;

and in response to the first usage (time t) map indicating that the corresponding storage unit (transmitting control information) of the second set (following steps) does not contain valid data , reading the data item from the storage unit of the first set . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (following steps) , each storage unit of the third set corresponding to one of the storage units of the first set (more memory) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transmitting control information) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time that is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transmitting control information) of the third set contains valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time that is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (following steps) of the third set contain valid data . 		US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (more memory) ;

and in response to the second usage map indicating that the corresponding storage unit (transmitting control information) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time that is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (more memory) ;

and in response to the second usage map indicating that the corresponding storage unit (transmitting control information) of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (more memory) ;

and in response to the second usage map indicating that the corresponding storage unit (transmitting control information) of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , reading the data item from the storage unit of the first set . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (following steps) for which an indication of valid data is stored in the first usage (time t) map . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (following steps) of storage units (following steps) with the third set of storage units . 		US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (following steps) of the second set (following steps) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (following steps) ;

for each of the plurality of servers : providing a first set (more memory) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (time t) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units (following steps) and the first set (more memory) of private storage units for the server . 		US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (more memory) of private storage units (following steps) and the first usage (time t) map of a first server . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (following steps) are stored in a same storage device . 		US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (following steps) are stored a local storage device and the private storage units are stored in a remote storage device (first location) . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location (remote storage device) of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time that is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the private storage units (following steps) contain valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (following steps) of private storage units (following steps) , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (transmitting control information) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time that is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (following steps) contains valid data . 		US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (following steps) of the second set (following steps) contain valid data . 		US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set (more memory) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set (more memory) does not contain valid data , reading the data item from the shared storage unit . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (more memory) for which an indication of valid data is stored in the first usage (time t) map . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (more memory) of private storage units (following steps) with the second set (following steps) of private storage units . 		US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (following steps) of the first set (more memory) that contain valid data to those corresponding private storage units of the second set (following steps) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (more memory) of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (transmitting control information) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (following steps) are stored in a same storage device . 		US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (more memory) of storage units (following steps) is stored in a local storage device and the second set (following steps) of storage units is stored in a remote storage device (first location) . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location (remote storage device) of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time that is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transmitting control information) of the second set (following steps) contains valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (time t) map is initially reset to indicate that none of the storage units (following steps) of the second set (following steps) contain valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (more memory) , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit (transmitting control information) of the second set (following steps) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (more memory) , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit (transmitting control information) of the second set (following steps) does not contain valid data , to read the data item from the storage unit of the first set . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (following steps) , each storage unit of the third set corresponding to one of the storage units of the first set (more memory) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (more memory) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (transmitting control information) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time that is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transmitting control information) of the third set contains valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time that is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (following steps) of the third set contain valid data . 		US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (more memory) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transmitting control information) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time that is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (more memory) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transmitting control information) of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set (following steps) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (more memory) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transmitting control information) of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , to read the data item from the storage unit of the first set . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (following steps) for which an indication of valid data is stored in the first usage (time t) map . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (following steps) of storage units (following steps) with the third set of storage units . 		US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (following steps) of the second set (following steps) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (more memory) of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (transmitting control information) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5748914A
CLAIM 1 . A method for performing data transfers within a computer system , the method comprising the steps of : causing a controller to perform the steps of transmitting control information (corresponding storage unit) on a bus , the control information specifying a data transfer operation and a first location of data to be transferred ;
after transmitting the control information on the bus , performing the steps of determining a desired amount of data to be transferred in the data transfer operation ;
transmitting over the bus additional locations of data if the desired amount of data is greater than a predetermined amount of data ;
transmitting over the bus a terminate indication at a time t (first usage) hat is based on the desired amount of data to be transferred ;
causing a memory device to perform the steps of reading the control information on the bus ;
performing the specified data transfer operation on data stored at the first location ;
performing the specified data transfer operation on data stored at the additional locations when the desired amount of data is greater than the amount of data associated with the first location ;
continuing to perform the specified data transfer operation until detecting the terminate indication on the bus ;
ceasing to perform the data transfer operation at a time that is based on the time at which the terminate indication is detected .

US5748914A
CLAIM 6 . A method , for use in a memory controller , for maximizing usage of a bus that connects the memory controller to one or more memory (first set) devices , the method comprising the steps of : selecting an interleave pattern based on requests received for a plurality of data transfer operations ;
and for each data transfer operation of the plurality of data transfer operations transmitting control information over the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator over the bus that specifies when the data transfer operation is to begin .

US5748914A
CLAIM 17 . A memory controller configured to maximize usage of a bus that connects the memory controller to one or more memory devices , the memory controller comprising : a control unit configured to select an interleave pattern based on requests received for a plurality of data transfer operations ;
and an output unit coupled to the control unit and to the bus ;
the control unit being further configured to perform the following steps (second set, storage units) for each data transfer operation of the plurality of data transfer operations : transmitting control information through the output unit to the bus , wherein the control information specifies the data transfer operation ;
determining how much time must elapse between transmission of the control information and the start of the data transfer operation to provide the interleave pattern ;
and transmitting a start indicator through the output unit to the bus , wherein the start indicator specifies when the data transfer operation is to begin .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		WO9613113A1

Filed: 1995-10-12     Issued: 1996-05-02

System and method for providing secure internetwork services

(Original Assignee) Secure Computing Corporation     

William E. Boebert, Clyde O. Rogers, Glenn Andreas, Scott W. Hammond, Mark P. Gooderum
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set (access rights) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set (access rights) of storage units is stored in a remote storage device (transferring data) . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set (access rights) contains valid data . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (access rights) contain valid data . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set (access rights) contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set (access rights) does not contain valid data , reading the data item from the storage unit of the first set . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the third set contains valid data . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (access rights) contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (access rights) does not contain valid data , reading the data item from the storage unit of the first set . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (access rights) for which an indication of valid data is stored in the first usage map . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (access rights) of storage units with the third set of storage units . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (access rights) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (kernel code) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		WO9613113A1
CLAIM 3 . The system according to claim 1 wherein the security policy program code comprises program code for hardening a UNIX operating system . , wherein the program code for hardening the UNIX operating system comprises kernel code (file systems) for enforcing Type Enforcement via an operational kernel .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (transferring data) . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (access rights) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (access rights) contains valid data . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (access rights) contain valid data . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (access rights) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (access rights) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (access rights) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units with the second set (access rights) of private storage units . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set (access rights) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (access rights) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module (limiting access) for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access (interception module) to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set (access rights) of storage units is stored in a remote storage device (transferring data) . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set (access rights) contains valid data . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (access rights) contain valid data . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module (limiting access) is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set (access rights) contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access (interception module) to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module (limiting access) is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set (access rights) does not contain valid data , to read the data item from the storage unit of the first set . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access (interception module) to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module (limiting access) is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (transferring data) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access (interception module) to data based on both user access rights and process access rights .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the third set contains valid data . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module (limiting access) is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access (interception module) to data based on both user access rights and process access rights .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module (limiting access) is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (access rights) contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access (interception module) to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module (limiting access) is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (access rights) does not contain valid data , to read the data item from the storage unit of the first set . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access (interception module) to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (access rights) for which an indication of valid data is stored in the first usage map . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (access rights) of storage units with the third set of storage units . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (access rights) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (access rights) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9613113A1
CLAIM 9 . A secure server , comprising : a processor (80) ;
an internal network interface (90) , connected to the processor , for communicating on an internal network ;
and an external network interface (96) , connected to the processor , for communicating on an external network ;
wherein the processor includes server program code (92) for transferring data (remote storage device, corresponding storage unit) between the internal and external network interfaces and security policy program code for enforcing a Type Enforcement security mechanism to restrict access of a process received from the external network to data stored on the internal network .

WO9613113A1
CLAIM 16 . The system according to claim 14 wherein the first secure computer is a type enforcing secure computer capable of recognizing data of varying sensitivity and of limiting access to data based on both user access rights (second set) and process access rights .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5907672A

Filed: 1995-10-04     Issued: 1999-05-25

System for backing up computer disk volumes with error remapping of flawed memory addresses

(Original Assignee) STAC Inc     (Current Assignee) Veritas Technologies LLC

John E. G. Matze, Douglas L. Whiting
US6618736B1
CLAIM 1 . A method for file system (temporary storage means) creation (temporary storage means) and archival comprising : providing a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US5907672A
CLAIM 42 . The method of any of claims 21-26 wherein writes to said disk volume are allowed by caching said writes to a temporary storage means (file system creation, file system) .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (following steps) are stored in a same storage device . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (following steps) is stored in a local storage device and the second set (following steps) of storage units is stored in a remote storage device . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (following steps) contains valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (following steps) of the second set (following steps) contain valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , reading the data item from the storage unit of the first set . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (following steps) , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (following steps) of the third set contain valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , reading the data item from the storage unit of the first set . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (following steps) for which an indication of valid data is stored in the first usage map . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (following steps) of storage units (following steps) with the third set of storage units . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (following steps) of the second set (following steps) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (following steps) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (temporary storage means) of each server comprises a combination of the set of shared storage units (following steps) and the first set of private storage units for the server . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US5907672A
CLAIM 42 . The method of any of claims 21-26 wherein writes to said disk volume are allowed by caching said writes to a temporary storage means (file system creation, file system) .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (following steps) and the first usage map of a first server . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (temporary storage means) for a second server using the stored template . 		US5907672A
CLAIM 42 . The method of any of claims 21-26 wherein writes to said disk volume are allowed by caching said writes to a temporary storage means (file system creation, file system) .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (following steps) are stored in a same storage device . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (following steps) are stored a local storage device and the private storage units are stored in a remote storage device . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (following steps) contain valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (following steps) of private storage units (following steps) , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (following steps) contains valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (following steps) of the second set (following steps) contain valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (following steps) with the second set (following steps) of private storage units . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (following steps) of the first set that contain valid data to those corresponding private storage units of the second set (following steps) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (temporary storage means) within at least one storage device comprising a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US5907672A
CLAIM 42 . The method of any of claims 21-26 wherein writes to said disk volume are allowed by caching said writes to a temporary storage means (file system creation, file system) .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (following steps) are stored in a same storage device . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (following steps) is stored in a local storage device and the second set (following steps) of storage units is stored in a remote storage device . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (following steps) contains valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (following steps) of the second set (following steps) contain valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5907672A
CLAIM 1 . A method for backing up data in a computer system from a primary storage means to a backup storage means on a sector-by-sector basis and restoring data in a computer system from said backup storage means to a restore storage means on a sector-by-sector basis , said method comprising the steps of : reading a set of logically contiguous sectors from the primary storage means using a software call of the operating system that provides access (storage unit reading module, storage unit update module) to the files stored on said primary storage means , said call of said operating system performing any physical level remapping necessary to avoid previously detected physical flaws on said primary storage means , writing said set of logically contiguous sectors to said backup storage means , creating a partition on said restore storage means of a size at least as large as the size of said primary storage means , reading a set of logically contiguous sectors from a location on said backup storage means , writing said set of logically contiguous sectors to said partition of said restore storage means using a software call to the operating system that provides access to the files stored on said partition of said restore storage means , said call of said operating system performing any physical level remapping necessary to detect and avoid physical flaws on said restore storage means .

US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , to read the data item from the storage unit of the first set . 		US5907672A
CLAIM 1 . A method for backing up data in a computer system from a primary storage means to a backup storage means on a sector-by-sector basis and restoring data in a computer system from said backup storage means to a restore storage means on a sector-by-sector basis , said method comprising the steps of : reading a set of logically contiguous sectors from the primary storage means using a software call of the operating system that provides access (storage unit reading module, storage unit update module) to the files stored on said primary storage means , said call of said operating system performing any physical level remapping necessary to avoid previously detected physical flaws on said primary storage means , writing said set of logically contiguous sectors to said backup storage means , creating a partition on said restore storage means of a size at least as large as the size of said primary storage means , reading a set of logically contiguous sectors from a location on said backup storage means , writing said set of logically contiguous sectors to said partition of said restore storage means using a software call to the operating system that provides access to the files stored on said partition of said restore storage means , said call of said operating system performing any physical level remapping necessary to detect and avoid physical flaws on said restore storage means .

US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (following steps) , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (following steps) of the third set contain valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5907672A
CLAIM 1 . A method for backing up data in a computer system from a primary storage means to a backup storage means on a sector-by-sector basis and restoring data in a computer system from said backup storage means to a restore storage means on a sector-by-sector basis , said method comprising the steps of : reading a set of logically contiguous sectors from the primary storage means using a software call of the operating system that provides access (storage unit reading module, storage unit update module) to the files stored on said primary storage means , said call of said operating system performing any physical level remapping necessary to avoid previously detected physical flaws on said primary storage means , writing said set of logically contiguous sectors to said backup storage means , creating a partition on said restore storage means of a size at least as large as the size of said primary storage means , reading a set of logically contiguous sectors from a location on said backup storage means , writing said set of logically contiguous sectors to said partition of said restore storage means using a software call to the operating system that provides access to the files stored on said partition of said restore storage means , said call of said operating system performing any physical level remapping necessary to detect and avoid physical flaws on said restore storage means .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5907672A
CLAIM 1 . A method for backing up data in a computer system from a primary storage means to a backup storage means on a sector-by-sector basis and restoring data in a computer system from said backup storage means to a restore storage means on a sector-by-sector basis , said method comprising the steps of : reading a set of logically contiguous sectors from the primary storage means using a software call of the operating system that provides access (storage unit reading module, storage unit update module) to the files stored on said primary storage means , said call of said operating system performing any physical level remapping necessary to avoid previously detected physical flaws on said primary storage means , writing said set of logically contiguous sectors to said backup storage means , creating a partition on said restore storage means of a size at least as large as the size of said primary storage means , reading a set of logically contiguous sectors from a location on said backup storage means , writing said set of logically contiguous sectors to said partition of said restore storage means using a software call to the operating system that provides access to the files stored on said partition of said restore storage means , said call of said operating system performing any physical level remapping necessary to detect and avoid physical flaws on said restore storage means .

US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (provides access) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , to read the data item from the storage unit of the first set . 		US5907672A
CLAIM 1 . A method for backing up data in a computer system from a primary storage means to a backup storage means on a sector-by-sector basis and restoring data in a computer system from said backup storage means to a restore storage means on a sector-by-sector basis , said method comprising the steps of : reading a set of logically contiguous sectors from the primary storage means using a software call of the operating system that provides access (storage unit reading module, storage unit update module) to the files stored on said primary storage means , said call of said operating system performing any physical level remapping necessary to avoid previously detected physical flaws on said primary storage means , writing said set of logically contiguous sectors to said backup storage means , creating a partition on said restore storage means of a size at least as large as the size of said primary storage means , reading a set of logically contiguous sectors from a location on said backup storage means , writing said set of logically contiguous sectors to said partition of said restore storage means using a software call to the operating system that provides access to the files stored on said partition of said restore storage means , said call of said operating system performing any physical level remapping necessary to detect and avoid physical flaws on said restore storage means .

US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (following steps) for which an indication of valid data is stored in the first usage map . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (following steps) of storage units (following steps) with the third set of storage units . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (following steps) of the second set (following steps) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (provides access) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5907672A
CLAIM 1 . A method for backing up data in a computer system from a primary storage means to a backup storage means on a sector-by-sector basis and restoring data in a computer system from said backup storage means to a restore storage means on a sector-by-sector basis , said method comprising the steps of : reading a set of logically contiguous sectors from the primary storage means using a software call of the operating system that provides access (storage unit reading module, storage unit update module) to the files stored on said primary storage means , said call of said operating system performing any physical level remapping necessary to avoid previously detected physical flaws on said primary storage means , writing said set of logically contiguous sectors to said backup storage means , creating a partition on said restore storage means of a size at least as large as the size of said primary storage means , reading a set of logically contiguous sectors from a location on said backup storage means , writing said set of logically contiguous sectors to said partition of said restore storage means using a software call to the operating system that provides access to the files stored on said partition of said restore storage means , said call of said operating system performing any physical level remapping necessary to detect and avoid physical flaws on said restore storage means .

US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (temporary storage means) within at least one storage device comprising a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5907672A
CLAIM 14 . The method of claim 13 wherein detection of changed sectors further includes the following steps (second set, storage units) : computing a checksum (or similar type of function) on groups of sectors read from said primary storage means , comparing said checksum with the corresponding checksum stored from the previous backup , operative when the two checksums do not match , writing said group of sectors to said backup storage means , writing said checksum to said backup storage means , operative when the two checksums do match , setting the entry (or entries) in said sector directory table corresponding to said group of sectors to point to the corresponding group of sectors from said previous backup .

US5907672A
CLAIM 42 . The method of any of claims 21-26 wherein writes to said disk volume are allowed by caching said writes to a temporary storage means (file system creation, file system) .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5764963A

Filed: 1995-09-20     Issued: 1998-06-09

Method and apparatus for performing maskable multiple color block writes

(Original Assignee) Rambus Inc     (Current Assignee) Rambus Inc

Frederick Abbott Ware, Richard Maurice Barth, Craig Hampel, John Bradly Dillon, Billy W. Garrett
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map (memory block) for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (following steps) are stored in a same storage device . 		US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (following steps) is stored in a local storage device and the second set (following steps) of storage units is stored in a remote storage device . 		US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (following steps) contains valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map (memory block) comprises : initializing the first usage map to indicate that none of the storage units (following steps) of the second set (following steps) contain valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map (memory block) indicating that the corresponding storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map (memory block) indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , reading the data item from the storage unit of the first set . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (following steps) , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map (memory block) for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map (memory block) comprises : initializing the second usage map to indicate that none of the storage units (following steps) of the third set contain valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map (memory block) indicating that the corresponding storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map (memory block) indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , reading the data item from the storage unit of the first set . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (following steps) for which an indication of valid data is stored in the first usage map (memory block) . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (following steps) of storage units (following steps) with the third set of storage units . 		US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (following steps) of the second set (following steps) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map (memory block) . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (following steps) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map (memory block) for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units (following steps) and the first set of private storage units for the server . 		US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (following steps) and the first usage map (memory block) of a first server . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (following steps) are stored in a same storage device . 		US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (following steps) are stored a local storage device and the private storage units are stored in a remote storage device . 		US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map (memory block) comprises : initializing the first usage map to indicate that none of the private storage units (following steps) contain valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage map (memory block) indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage map (memory block) indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (following steps) of private storage units (following steps) , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map (memory block) for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (following steps) contains valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map (memory block) comprises : initializing the second usage map to indicate that none of the private storage units (following steps) of the second set (following steps) contain valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map (memory block) indicating that the corresponding private storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map (memory block) indicating that the corresponding private storage unit of the second set (following steps) does not contain valid data and the first usage map (memory block) indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map (memory block) indicating that the corresponding private storage unit of the second set (following steps) does not contain valid data and the first usage map (memory block) indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set for which an indication of valid data is stored in the first usage map (memory block) . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (following steps) with the second set (following steps) of private storage units . 		US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (following steps) of the first set that contain valid data to those corresponding private storage units of the second set (following steps) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map (memory block) . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map (memory block) for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (Memory apparatus) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module (memory block) for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5764963A
CLAIM 1 . Memory apparatus (storage unit writing module) for performing a maskable , multiple color block write , comprising : a mask register ;
a block of memory having pixel addresses , wherein each pixel address corresponds to at least two mask value bits stored in the mask register ;
a plurality of color registers ;
control circuitry for selecting pixel addresses in accordance with their corresponding mask value bits in response to a block write signal , wherein a color value for each selected pixel address is selected from one of the plurality of color registers in accordance with the corresponding mask value bits , wherein the selected color values are written to the selected pixel addresses substantially simultaneously .

US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (following steps) are stored in a same storage device . 		US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (following steps) is stored in a local storage device and the second set (following steps) of storage units is stored in a remote storage device . 		US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (following steps) contains valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map (memory block) is initially reset to indicate that none of the storage units (following steps) of the second set (following steps) contain valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map (memory block) indicating that the corresponding storage unit of the second set (following steps) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map (memory block) indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , to read the data item from the storage unit of the first set . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (following steps) , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map (memory block) for indicating which storage units of third set contain valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module (Memory apparatus) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module (memory block) is further configured to store an indication in the second usage map (memory block) that the corresponding storage unit of the third set contains valid data . 		US5764963A
CLAIM 1 . Memory apparatus (storage unit writing module) for performing a maskable , multiple color block write , comprising : a mask register ;
a block of memory having pixel addresses , wherein each pixel address corresponds to at least two mask value bits stored in the mask register ;
a plurality of color registers ;
control circuitry for selecting pixel addresses in accordance with their corresponding mask value bits in response to a block write signal , wherein a color value for each selected pixel address is selected from one of the plurality of color registers in accordance with the corresponding mask value bits , wherein the selected color values are written to the selected pixel addresses substantially simultaneously .

US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map (memory block) is initially reset to indicate that none of the storage units (following steps) of the third set contain valid data . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map (memory block) indicating that the corresponding storage unit of the second set (following steps) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map (memory block) indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , to read the data item from the storage unit of the first set . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (following steps) for which an indication of valid data is stored in the first usage map (memory block) . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (following steps) of storage units (following steps) with the third set of storage units . 		US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (following steps) of the second set (following steps) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map (memory block) . 		US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map (memory block) for indicating which storage units of the second set contain valid data ;

program code (write signal) for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5764963A
CLAIM 1 . Memory apparatus for performing a maskable , multiple color block write , comprising : a mask register ;
a block of memory having pixel addresses , wherein each pixel address corresponds to at least two mask value bits stored in the mask register ;
a plurality of color registers ;
control circuitry for selecting pixel addresses in accordance with their corresponding mask value bits in response to a block write signal (program code) , wherein a color value for each selected pixel address is selected from one of the plurality of color registers in accordance with the corresponding mask value bits , wherein the selected color values are written to the selected pixel addresses substantially simultaneously .

US5764963A
CLAIM 6 . The apparatus of claim 1 wherein the memory block (first usage map, second usage map, usage map updating module) further comprises interfacing circuitry having a plurality of data pins for accessing the block of memory , wherein each data pin is associated with a distinct byte of the block of memory , wherein the interfacing circuitry is coupled to the control circuitry .

US5764963A
CLAIM 7 . A method of performing a maskable , multiple color block write , comprising the steps of : a) storing a mask value within a mask register , wherein each pixel address within a block of memory corresponds to at least two mask value bits ;
b) selecting pixel addresses from the block of memory in accordance with the corresponding mask value bits ;
c) performing the following steps (second set, storage units) for each selected pixel address substantially simultaneously : i) selecting a color value in accordance with the corresponding mask value bits for that selected pixel address ;
ii) writing the color value to the selected pixel address .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5619644A

Filed: 1995-09-18     Issued: 1997-04-08

Software directed microcode state save for distributed storage controller

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Robert N. Crockett, Ronald M. Kern, William F. Micka
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set (including one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set (including one) of storage units is stored in a remote storage device . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (including one) contains valid data . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (including one) contain valid data . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (including one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (including one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (including one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (including one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (including one) for which an indication of valid data is stored in the first usage map . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (including one) of storage units with the third set of storage units . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (including one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (system error) (secondary data) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5619644A
CLAIM 1 . In a storage system having distributed system components including a host processor running software applications therein generating record updates and having a data mover , said host processor coupled to a first storage controller , wherein an error condition occurs in said storage system , said data mover executing a machine effected method for coordinating problem determinations amongst said distributed system components , said machine effected method comprising steps of : (a) issuing I/O operations for record updates generated by said software applications ;
(b) storing said record updates in said first storage controller according to said issued I/O operations ;
(c) maintaining control information associated with said record updates in said first storage controller ;
(d) reading said record updates and associated control information into said data mover from said first storage controller in preparation for remotely copying said record updates ;
(e) detecting the storage system error (file systems) condition in said data mover ;
(f) issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said first storage controller ;
(g) capturing failure information in said host processor and said first storage controller ;
and (h) correlating said failure information in said host processor with said failure information in said first storage controller according to said storage system error condition , wherein said diagnostic state save channel command word temporarily suspends operations in said host processor and said storage controller until after said failure information is captured and correlated between said host processor and said first storage controller .

US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (including one) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (including one) contains valid data . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (including one) contain valid data . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (including one) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (including one) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (including one) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units with the second set (including one) of private storage units . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set (including one) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (including one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set (including one) of storage units is stored in a remote storage device . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (including one) contains valid data . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (including one) contain valid data . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (including one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (including one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (including one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (including one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (including one) for which an indication of valid data is stored in the first usage map . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (including one) of storage units with the third set of storage units . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (including one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (including one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5619644A
CLAIM 9 . A computer readable storage medium for storing a data mover application for causing state save diagnostics to be merged across multiple system components in response to a storage system error , said system components including a host processor coupled to a storage controller for managing record updates generated by software applications to a direct access storage device (data item) (DASD) , said data mover application comprising : means for issuing I/O operations for record updates generated in said software applications ;
means for storing said record updates in said first storage controller according to said issued I/O operations ;
maintenance means for maintaining control information associated with said record updates in said storage controller ;
reading means for reading said record updates and associated control information into said data mover in preparation for remotely copying said record updates ;
detecting means for detecting a storage system error condition and communicating said error condition to said data mover ;
state save means for issuing a diagnostic state save channel command word (CCW) from said data mover to said host processor and said storage controller ;
capture means for capturing failure information in said host processor and said storage controller ;
and correlating means for correlating said failure information in each system component of said multiple system components according to the detected error condition .

US5619644A
CLAIM 14 . A data storage system for coordinating failure information amongst system components associated with an error condition occurring in said data storage system , said system components including one (second set) or more storage controllers coupled to non-volatile storage devices for storing record updates thereon , said data storage system comprising : a host processor running software applications thereon , said applications generating the record updates and transmitting I/O operations to said one or more storage controllers for eventual storage on said non-volatile storage devices , said host processor further including a first data mover for reading said record updates from said one or more storage controllers and assembling said record updates into groups for transmission to a remote storage system for disaster recovery purposes , said data mover receiving an error code from one of said system components indicating a type of error condition that occurred , said data mover issuing a State Save command to those system components associated with said error condition , said State Save command causing said associated system components to temporarily suspend processing record updates for collecting failure information , said failure information being correlated amongst said system components according to the State Save command , said data mover further comprising : a trace queue for storing failure information associated with said data mover ;
a control section for managing record updates read into said data mover ;
and a plurality of buffers for storing said record updates and header information associated with said record updates .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		JPH08227394A

Filed: 1995-07-04     Issued: 1996-09-03

データ処理システム及びその動作方法

(Original Assignee) Monolithic Syst Technol Inc; モノリシック・システム・テクノロジー・インコーポレイテッド     

Fu-Chien Hsu, Winston Lee, Wingyu Leung, ウィング・リュング, ウィンストン・リー, フー−チア・スー
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set (インタリー) of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (シーケンス) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets (１セット) of storage units are stored in a same storage device . 		JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。
US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device (少なくとも) and the second set (インタリー) of storage units is stored in a remote storage device . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the second set (インタリー) contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (インタリー) contain valid data . 		JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (シーケンス) from a storage unit (少なくとも) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (インタリー) contains valid data , reading the data item from the corresponding storage unit of the second set . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (シーケンス) from a storage unit (少なくとも) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (インタリー) does not contain valid data , reading the data item from the storage unit of the first set . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (１セット) of storage units , each storage unit (少なくとも) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (シーケンス) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。
US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the third set (１セット) contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。
US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (１セット) contain valid data . 		JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。
US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (シーケンス) from a storage unit (少なくとも) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (１セット) contains valid data , reading the data item from the corresponding storage unit of the third set . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。
US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (シーケンス) from a storage unit (少なくとも) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (１セット) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (インタリー) contains valid data , reading the data item from the corresponding storage unit of the second set . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (シーケンス) from a storage unit (少なくとも) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (１セット) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (インタリー) does not contain valid data , reading the data item from the storage unit of the first set . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (少なくとも) of the second set (インタリー) for which an indication of valid data is stored in the first usage map . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (インタリー) of storage units with the third set (１セット) of storage units . 		JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (インタリー) that contain valid data to those corresponding storage units of the third set (１セット) that do not contain valid data ;

and for each storage unit (少なくとも) of the second set that is copied , storing an indication of valid data in the second usage map . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (少なくとも) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (シーケンス) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。
US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device (少なくとも) and the private storage units are stored in a remote storage device . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。
US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (少なくとも) contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。
US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (シーケンス) from a shared storage unit (少なくとも) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。
US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (シーケンス) from a shared storage unit (少なくとも) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。
US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (インタリー) of private storage units , each private storage unit (少なくとも) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (シーケンス) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (少なくとも) of the second set (インタリー) contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (インタリー) contain valid data . 		JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (シーケンス) from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (インタリー) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (シーケンス) from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (インタリー) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (シーケンス) from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (インタリー) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (少なくとも) of the first set for which an indication of valid data is stored in the first usage map . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。
US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units with the second set (インタリー) of private storage units . 		JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set (インタリー) that do not contain valid data ;

and for each private storage unit (少なくとも) of the first set that is copied , storing an indication of valid data in the second usage map . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (インタリー) of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (シーケンス) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets (１セット) of storage units are stored in a same storage device . 		JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。
US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device (少なくとも) and the second set (インタリー) of storage units is stored in a remote storage device . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the second set (インタリー) contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (インタリー) contain valid data . 		JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (シーケンス) from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (インタリー) contains valid data , to read the data item from the corresponding storage unit of the second set . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 30 【請求項３０】 前記前記 (storage unit reading module) Ｉ／Ｏバスが、更に、シス テムクロック信号と電力とを伝送するバスラインの第３ セットを含むことを特徴とする請求項２８に記載のデー タ処理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (シーケンス) from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (インタリー) does not contain valid data , to read the data item from the storage unit of the first set . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 30 【請求項３０】 前記前記 (storage unit reading module) Ｉ／Ｏバスが、更に、シス テムクロック信号と電力とを伝送するバスラインの第３ セットを含むことを特徴とする請求項２８に記載のデー タ処理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (１セット) of storage units , each storage unit (少なくとも) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。
US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (シーケンス) to a storage unit (少なくとも) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (１セット) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。
US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the third set (１セット) contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。
US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (１セット) contain valid data . 		JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。
US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (シーケンス) from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (１セット) contains valid data , to read the data item from the corresponding storage unit of the third set . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。

JPH08227394A
CLAIM 30 【請求項３０】 前記前記 (storage unit reading module) Ｉ／Ｏバスが、更に、シス テムクロック信号と電力とを伝送するバスラインの第３ セットを含むことを特徴とする請求項２８に記載のデー タ処理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。
US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (シーケンス) from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (１セット) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (インタリー) contains valid data , to read the data item from the corresponding storage unit of the second set . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。

JPH08227394A
CLAIM 30 【請求項３０】 前記前記 (storage unit reading module) Ｉ／Ｏバスが、更に、シス テムクロック信号と電力とを伝送するバスラインの第３ セットを含むことを特徴とする請求項２８に記載のデー タ処理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (シーケンス) from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (１セット) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (インタリー) does not contain valid data , to read the data item from the storage unit of the first set . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。

JPH08227394A
CLAIM 30 【請求項３０】 前記前記 (storage unit reading module) Ｉ／Ｏバスが、更に、シス テムクロック信号と電力とを伝送するバスラインの第３ セットを含むことを特徴とする請求項２８に記載のデー タ処理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (少なくとも) of the second set (インタリー) for which an indication of valid data is stored in the first usage map . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (インタリー) of storage units with the third set (１セット) of storage units . 		JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (インタリー) that contain valid data to those corresponding storage units of the third set (１セット) that do not contain valid data ;

and wherein the storage unit (少なくとも) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 28 【請求項２８】 前記Ｉ／Ｏバスが、制御情報を伝送 するバスラインの第１セット (second sets, third set) と、多重化されたデータ、 アドレス、及び制御情報を伝送するバスラインの第２セ ットとを含むことを特徴とする請求項２７に記載のデー タ処理システム。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。
US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (インタリー) of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (シーケンス) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH08227394A
CLAIM 10 【請求項１０】 前記バスラインの少なくとも (storage unit, local storage device) 一つ が、前記バス上の信号伝送の同期のためのクロック信号 を伝送することを特徴とする請求項９に記載のデータ処 理システム。

JPH08227394A
CLAIM 73 【請求項７３】 アドレスシーケンス (data item) 回路であって、 初期列アドレス信号を受信すると共に、この初期列アド レス信号をデコードしてデコードされた初期列アドレス 信号を提供するためのデコード回路と、 前記デコードされた初期列アドレス信号を受信するため のバレルシフタ回路であって、該バレルシフタ回路は、 ロード信号に応答して前記デコードされた初期列アドレ ス信号をローディングされ、更にクロック信号に応答し て列選択信号を順次発生する該バレルシフタ回路と、 前記バレルシフタ回路から前記列選択信号を受信して、 前記列選択信号をメモリアレイの列制御回路へと伝達す るバッファ回路とを含むことを特徴とするアドレスシー ケンス回路。

JPH08227394A
CLAIM 78 【請求項７８】 パスに並列に接続された選択された 複数のメモリデバイスからデータを読み取る方法であっ て、 前記選択された複数のメモリデバイスの各々内のインタ リーブイネーブルビットをセットするように、前記バス 上にインタリー (second set) ブアクセス選択コマンドを発する過程 と、 前記バス上に行アクセスコマンドを発することによっ て、前記選択された複数のメモリデバイスの各々に於い て行アクセス動作を同時に実行する過程と、 前記選択された複数のメモリデバイスの各々内で列アク セス動作が代わるがわる実行されるように前記バス上に 読み取りコマンドを発することによって、前記メモリデ バイスから前記バスへとデータが時間多重化されて代わ るがわる読み取られる過程とを含むことを特徴とする方 法。



US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5560000A

Filed: 1995-06-07     Issued: 1996-09-24

Time skewing arrangement for operating memory in synchronism with a data processor

(Original Assignee) Texas Instruments Inc     (Current Assignee) Texas Instruments Inc

Wilbur C. Vogley
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (time t) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage (time t) map . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (time t) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage (time t) map of a first server . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set for which an indication of valid data is stored in the first usage (time t) map . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (write operation) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5560000A
CLAIM 1 . A circuit for a data processing system , the circuit comprising : an address register , interconnected with a plurality of synchronous random access memory devices and arranged for receiving and storing synchronous random access memory address information ;
a control signal register , interconnected with the plurality of synchronous random access memory devices and arranged for receiving and storing synchronous random access memory control signals ;
a data buffer register , interconnected with a memory clock delay circuit and the plurality of synchronous random access memory devices and arranged for receiving and storing data bits during a memory write operation (storage unit writing module) ;
and the memory clock delay circuit , interconnected with the address register , the control signal register , and the plurality of synchronous random access memory devices and responsive to a system clock signal and memory clock delay data , for producing a plurality of time skewed memory clock signals each one to be applied to a separate one of the synchronous random access memory devices , and each time skewed memory clock signal being delayed a different increment of time so that the plurality of synchronous random access memory devices each can operate at a different time in response to the one of the time skewed memory clock signals to accept the address information , the control signals , and data bits .

US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (time t) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module (write operation) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5560000A
CLAIM 1 . A circuit for a data processing system , the circuit comprising : an address register , interconnected with a plurality of synchronous random access memory devices and arranged for receiving and storing synchronous random access memory address information ;
a control signal register , interconnected with the plurality of synchronous random access memory devices and arranged for receiving and storing synchronous random access memory control signals ;
a data buffer register , interconnected with a memory clock delay circuit and the plurality of synchronous random access memory devices and arranged for receiving and storing data bits during a memory write operation (storage unit writing module) ;
and the memory clock delay circuit , interconnected with the address register , the control signal register , and the plurality of synchronous random access memory devices and responsive to a system clock signal and memory clock delay data , for producing a plurality of time skewed memory clock signals each one to be applied to a separate one of the synchronous random access memory devices , and each time skewed memory clock signal being delayed a different increment of time so that the plurality of synchronous random access memory devices each can operate at a different time in response to the one of the time skewed memory clock signals to accept the address information , the control signals , and data bits .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage (time t) map . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5560000A
CLAIM 3 . A circuit , in accordance with claim 1 , wherein : the memory clock delay circuit includes : a memory clock delay register , responsive to memory clock delay data and a memory delay data load signal , for storing the memory clock delay data to select an increment of memory clock delay time t (first usage) o be imparted into a memory clock signal ;
and a memory clock delay selector , responsive to the system clock signal and the memory clock delay data , for imparting the memory clock delay time into the memory clock signal .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5615358A

Filed: 1995-06-07     Issued: 1997-03-25

Time skewing arrangement for operating memory in synchronism with a data processor

(Original Assignee) Texas Instruments Inc     (Current Assignee) Texas Instruments Inc

Wilbur C. Vogley
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (different one) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (different one) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (different one) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (different one) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (different one) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (different one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (different one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (different one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (different one) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (different one) of private storage units for the server . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (different one) of private storage units and the first usage map of a first server . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (different one) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (different one) does not contain valid data , reading the data item from the shared storage unit . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (different one) for which an indication of valid data is stored in the first usage map . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (different one) of private storage units with the second set of private storage units . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (different one) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (different one) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (different one) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (different one) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit of the first set (different one) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (different one) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5615358A
CLAIM 1 . A data processing system comprising : a plurality of synchronous random access memory devices , each memory device including at least one array of memory cells ;
a digital processor for producing address signals , data signals , and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices ;
and a time skewing circuit , interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different one (first set) s of the synchronous random access memory devices , for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage device (data item) s included within the time skewing circuit , and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5604862A

Filed: 1995-03-14     Issued: 1997-02-18

Continuously-snapshotted protection of computer files

(Original Assignee) Network Integrity Inc     (Current Assignee) Autonomy Inc

Christopher W. Midgely, Charles J. Holland, John W. Webb, Manuel Gonsalves
US6618736B1
CLAIM 1 . A method for file system (file system) creation and archival comprising : providing a first set (current versions) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US5604862A
CLAIM 25 . In a computer data protection system , a method comprising the steps of : traversing a file system (file system) of a protected computer by a protection process , snapshotting files of said file system to removable storage media , and as each file is opened for said snapshotting , recording that the protection process currently holds the file open , and as the protection process completes said snapshotting , recording that the protection process has released the file ;
and when a client process requests access to a file , consulting said recording to determine whether the file is currently open by said protection process , and if the file is currently held open by said protection process , blocking said client process until said protection process releases the file , and if the file is not currently held open by said protection process , or when the protection process completes said snapshotting , proceeding to open the file in accord with the file open protocol of said protected computer .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets (minimum set) of storage units are stored in a same storage device . 		US5604862A
CLAIM 1 . A method for managing copies of a protected set of files on a bounded number of sequential-access volumes , the method being executed by computer and comprising : (a) from among a plurality of said sequential-access volumes , selecting one as the current volume ;
(b) when an external process independent of the sequential-access volumes alters the contents of one of the protected files to produce a new current version of the protected file , snapshotting the new current version of the altered protected file at the end of the current volume ;
(c) when the current volume is full to a defined limit , selecting a new volume to be the current volume ;
(d) maintaining the population of an active set of said sequential-access volumes at or below said bounded number , said active set being the minimum set (second sets) of the most-recently-current of said volumes that together contain at least one version of each of said protected files , by : as said population approaches or equals said bounded number , selecting for compaction one volume of said active set , and copying from the compaction volume to the current volume those versions of file versions stored on the compaction volume not having a more recent version stored on the active set ;
and (e) repeating steps (b)-(d) while the external process continues .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (current versions) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (current versions) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (current versions) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (file server) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (current versions) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (file server) contains valid data . 		US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (file server) contain valid data . 		US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (current versions) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (file server) contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (current versions) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (file server) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (current versions) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (file server) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units with the third set (file server) of storage units . 		US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set (file server) that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (current versions) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (file system) of each server comprises a combination of the set of shared storage units and the first set (current versions) of private storage units for the server . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 25 . In a computer data protection system , a method comprising the steps of : traversing a file system (file system) of a protected computer by a protection process , snapshotting files of said file system to removable storage media , and as each file is opened for said snapshotting , recording that the protection process currently holds the file open , and as the protection process completes said snapshotting , recording that the protection process has released the file ;
and when a client process requests access to a file , consulting said recording to determine whether the file is currently open by said protection process , and if the file is currently held open by said protection process , blocking said client process until said protection process releases the file , and if the file is not currently held open by said protection process , or when the protection process completes said snapshotting , proceeding to open the file in accord with the file open protocol of said protected computer .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (current versions) of private storage units and the first usage map of a first server . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (file system) for a second server using the stored template . 		US5604862A
CLAIM 25 . In a computer data protection system , a method comprising the steps of : traversing a file system (file system) of a protected computer by a protection process , snapshotting files of said file system to removable storage media , and as each file is opened for said snapshotting , recording that the protection process currently holds the file open , and as the protection process completes said snapshotting , recording that the protection process has released the file ;
and when a client process requests access to a file , consulting said recording to determine whether the file is currently open by said protection process , and if the file is currently held open by said protection process , blocking said client process until said protection process releases the file , and if the file is not currently held open by said protection process , or when the protection process completes said snapshotting , proceeding to open the file in accord with the file open protocol of said protected computer .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (current versions) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (current versions) does not contain valid data , reading the data item from the shared storage unit . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (current versions) for which an indication of valid data is stored in the first usage map . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (current versions) of private storage units with the second set of private storage units . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (current versions) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (file system) within at least one storage device comprising a first set (current versions) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US5604862A
CLAIM 25 . In a computer data protection system , a method comprising the steps of : traversing a file system (file system) of a protected computer by a protection process , snapshotting files of said file system to removable storage media , and as each file is opened for said snapshotting , recording that the protection process currently holds the file open , and as the protection process completes said snapshotting , recording that the protection process has released the file ;
and when a client process requests access to a file , consulting said recording to determine whether the file is currently open by said protection process , and if the file is currently held open by said protection process , blocking said client process until said protection process releases the file , and if the file is not currently held open by said protection process , or when the protection process completes said snapshotting , proceeding to open the file in accord with the file open protocol of said protected computer .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets (minimum set) of storage units are stored in a same storage device . 		US5604862A
CLAIM 1 . A method for managing copies of a protected set of files on a bounded number of sequential-access volumes , the method being executed by computer and comprising : (a) from among a plurality of said sequential-access volumes , selecting one as the current volume ;
(b) when an external process independent of the sequential-access volumes alters the contents of one of the protected files to produce a new current version of the protected file , snapshotting the new current version of the altered protected file at the end of the current volume ;
(c) when the current volume is full to a defined limit , selecting a new volume to be the current volume ;
(d) maintaining the population of an active set of said sequential-access volumes at or below said bounded number , said active set being the minimum set (second sets) of the most-recently-current of said volumes that together contain at least one version of each of said protected files , by : as said population approaches or equals said bounded number , selecting for compaction one volume of said active set , and copying from the compaction volume to the current volume those versions of file versions stored on the compaction volume not having a more recent version stored on the active set ;
and (e) repeating steps (b)-(d) while the external process continues .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (current versions) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (current versions) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (current versions) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (file server) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (current versions) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit of the first set (current versions) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (file server) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (file server) contains valid data . 		US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (file server) contain valid data . 		US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (current versions) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (file server) contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (current versions) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (file server) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (current versions) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (file server) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units with the third set (file server) of storage units . 		US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set (file server) that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5604862A
CLAIM 13 . The method of claim 1 , wherein : the altering of the file server (third set) s' ;
protected files includes creation of a file by the external process .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (file system) within at least one storage device comprising a first set (current versions) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5604862A
CLAIM 6 . The method of claim 1 , wherein : recently-compacted volumes are maintained as a legacy set of volumes containing additional copies of current versions (first set) and non-current versions of protected files , and storage records corresponding to the file versions stored on the legacy set are retained allowing prompt retrieval of those copies as requested by the external process .

US5604862A
CLAIM 14 . A method for protecting a protected set of files of varying size and stored on direct-access mass storage device (data item) s of a plurality of file server nodes of a network of computers , the method comprising : at a rate similar to the rate at which said files are altered by an external process , snapshotting recently-altered protected ones of said files from said direct-access mass storage devices to an archive storage cache , a new snapshot of a given file in said storage cache displacing any older snapshot of said given file in existence in said storage cache ;
copying , continuously but at a lower rate than said snapshotting that allows a significant proportion of said snapshotted versions to be displaced from said archive storage cache , non-displaced snapshotted versions from said storage cache to removable mass storage media .

US5604862A
CLAIM 25 . In a computer data protection system , a method comprising the steps of : traversing a file system (file system) of a protected computer by a protection process , snapshotting files of said file system to removable storage media , and as each file is opened for said snapshotting , recording that the protection process currently holds the file open , and as the protection process completes said snapshotting , recording that the protection process has released the file ;
and when a client process requests access to a file , consulting said recording to determine whether the file is currently open by said protection process , and if the file is currently held open by said protection process , blocking said client process until said protection process releases the file , and if the file is not currently held open by said protection process , or when the protection process completes said snapshotting , proceeding to open the file in accord with the file open protocol of said protected computer .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		JPH08202653A

Filed: 1995-01-27     Issued: 1996-08-09

並列信号伝送装置

(Original Assignee) Ricoh Co Ltd; 株式会社リコー     

Toshiharu Murai, 俊晴 村井
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units (繰り返し) and a second set of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (繰り返し) are stored in a same storage device . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (繰り返し) is stored in a local storage device (少なくとも) and the second set of storage units is stored in a remote storage device . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the second set contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (繰り返し) of the second set contain valid data . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (繰り返し) , each storage unit (少なくとも) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the third set contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (繰り返し) of the third set contain valid data . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (少なくとも) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (少なくとも) of the second set for which an indication of valid data is stored in the first usage map . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units (繰り返し) with the third set of storage units . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (繰り返し) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (少なくとも) of the second set that is copied , storing an indication of valid data in the second usage map . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (繰り返し) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (少なくとも) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units (繰り返し) and the first set of private storage units for the server . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (繰り返し) and the first usage map of a first server . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (繰り返し) are stored in a same storage device . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (繰り返し) are stored a local storage device (少なくとも) and the private storage units are stored in a remote storage device . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (少なくとも) contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (繰り返し) contain valid data . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units (繰り返し) , each private storage unit (少なくとも) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (少なくとも) of the second set contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (繰り返し) of the second set contain valid data . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (少なくとも) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (少なくとも) of the first set for which an indication of valid data is stored in the first usage map . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (繰り返し) with the second set of private storage units . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (繰り返し) of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (少なくとも) of the first set that is copied , storing an indication of valid data in the second usage map . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units (繰り返し) and a second set of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (繰り返し) are stored in a same storage device . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (繰り返し) is stored in a local storage device (少なくとも) and the second set of storage units is stored in a remote storage device . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the second set contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (繰り返し) of the second set contain valid data . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (繰り返し) , each storage unit (少なくとも) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (少なくとも) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (少なくとも) of the third set contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (繰り返し) of the third set contain valid data . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (少なくとも) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (少なくとも) of the second set for which an indication of valid data is stored in the first usage map . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。
US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units (繰り返し) with the third set of storage units . 		JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (繰り返し) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (少なくとも) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。
US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units (繰り返し) and a second set of storage units , each storage unit (少なくとも) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		JPH08202653A
CLAIM 5 【請求項５】請求項１，２，３または４記載の並列信号 伝送装置において、前記手段が一連の動作を少なくとも (storage unit, local storage device) 電源投入時に行うことを特徴とする並列信号伝送装置。

JPH08202653A
CLAIM 6 【請求項６】請求項１，２，３，４または５記載の並列 信号伝送装置において、前記手段が一連の動作を所定時 間毎に繰り返し (storage units, corresponding storage units) て行うことを特徴とする並列信号伝送装 置。



US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5649152A

Filed: 1994-10-13     Issued: 1997-07-15

Method and system for providing a static snapshot of data stored on a mass storage system

(Original Assignee) Vinca Corp     (Current Assignee) EMC Corp

Richard S. Ohran, Michael R. Ohran
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (following steps) are stored in a same storage device . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (following steps) is stored in a local storage device and the second set (following steps) of storage units is stored in a remote storage device . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (following steps) contains valid data . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (following steps) of the second set (following steps) contain valid data . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , reading the data item from the storage unit of the first set . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (file server) of storage units (following steps) , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (file server) contains valid data . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (following steps) of the third set (file server) contain valid data . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (file server) contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (file server) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (file server) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , reading the data item from the storage unit of the first set . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (following steps) for which an indication of valid data is stored in the first usage map . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (following steps) of storage units (following steps) with the third set (file server) of storage units . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (following steps) of the second set (following steps) that contain valid data to those corresponding storage units of the third set (file server) that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (following steps) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units (following steps) and the first set of private storage units for the server . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (following steps) and the first usage map of a first server . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (following steps) are stored in a same storage device . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (following steps) are stored a local storage device and the private storage units are stored in a remote storage device . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (following steps) contain valid data . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (following steps) of private storage units (following steps) , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (following steps) contains valid data . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (following steps) of the second set (following steps) contain valid data . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (following steps) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (following steps) with the second set (following steps) of private storage units . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (following steps) of the first set that contain valid data to those corresponding private storage units of the second set (following steps) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (following steps) are stored in a same storage device . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (following steps) is stored in a local storage device and the second set (following steps) of storage units is stored in a remote storage device . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (following steps) contains valid data . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (following steps) of the second set (following steps) contain valid data . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , to read the data item from the storage unit of the first set . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (file server) of storage units (following steps) , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (file server) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (file server) contains valid data . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (following steps) of the third set (file server) contain valid data . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (file server) contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (file server) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (file server) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (following steps) does not contain valid data , to read the data item from the storage unit of the first set . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (following steps) for which an indication of valid data is stored in the first usage map . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (following steps) of storage units (following steps) with the third set (file server) of storage units . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (following steps) of the second set (following steps) that contain valid data to those corresponding storage units of the third set (file server) that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5649152A
CLAIM 16 . A method as in claim 1 , wherein said digital computer acts as a file server (third set) , and said virtual device is exported to other computers .

US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units (following steps) and a second set (following steps) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5649152A
CLAIM 23 . In a computer system having a processor , a mass storage system for storing blocks of data in response to write operations , and a preservation memory means , a method of providing a static snapshot of the mass storage system at a particular point in time so that said static snapshot does not change even though the contents of said mass storage system change , the method comprising the steps of : clearing the preservation memory means so that the preservation memory means is ready to preserve data blocks of said mass storage system : preserving a snapshot of the mass storage system at a particular point in time by executing at least the following steps (second set, storage units) : (1) when a data block is to be over-written by a new data block at said same write address , checking said preservation memory means to determine if the data block specified by said address has already been stored in the preservation memory means ;
(2) if and only if said data block has already been stored in said preservation memory means , performing the over-write operation so that said new data block replaces the data block at said address ;
and (3) if the data block that is to be overwritten has not been already stored in said preservation memory means , preserving the data block by first copying said data block into said preservation memory means prior to performing the over-write operation , thereby permitting said mass storage system to be updated as each data block is preserved at a given snapshot moment in the preservation memory means .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5422858A

Filed: 1994-06-16     Issued: 1995-06-06

Semiconductor integrated circuit

(Original Assignee) Hitachi ULSI Engineering Corp; Hitachi Ltd     (Current Assignee) Hitachi ULSI Engineering Corp ; Renesas Electronics Corp

Masao Mizukami, Yoichi Sato, Takahiko Kozaki, Satoshi Shinagawa
US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (read gate) . 		US5422858A
CLAIM 4 . A semiconductor integrated circuit according to claim 2 , wherein the first circuit area is a spread gate (remote storage device) area whose required function is practically attained on the basis of the form of connecting numerous basic circuits repetitively and wherein the second circuit area is a macro cell whose required function is practically attained by making the integration of circuit elements therein greater than that of those in the spread gate area .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (read gate) . 		US5422858A
CLAIM 4 . A semiconductor integrated circuit according to claim 2 , wherein the first circuit area is a spread gate (remote storage device) area whose required function is practically attained on the basis of the form of connecting numerous basic circuits repetitively and wherein the second circuit area is a macro cell whose required function is practically attained by making the integration of circuit elements therein greater than that of those in the spread gate area .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (write operation) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5422858A
CLAIM 8 . A semiconductor integrated circuit comprising : a first circuit area operating in synchronization with a first clock signal , a second circuit area which is capable of operating in synchronization with a clock signal whose frequency is higher than that of the first clock signal and has a memory array and access ports for writing and reading data simultaneously to and from the memory array , and a rate conversion circuit area for making the second circuit area accessible from the first circuit area , wherein the first circuit area is a spread gate area whose required function is practically attained on the basis of the form of connecting numerous basic circuits repetitively and the second circuit area is a macro cell whose required function is practically attained by making the integration of circuit elements therein greater than that of those in the spread gate area , the rate conversion circuit area further comprises a multiplied clock generator circuit for receiving an access control signal for allowing the first circuit area to gain access to the second circuit area and the first clock signal from the first circuit area , and forming a second clock signal whose frequency is multiplied an optional number of times that of the first clock signal according to the first clock signal and read/write signals for sequentially designating a read operation in synchronization with the second clock signal and the following write operation (storage unit writing module) so as to supply these signals to the second circuit area when the read and write operations are designated in parallel according to the access control signal , a parallel-serial conversion circuit for receiving memory access data for writing and reading in parallel from the first circuit area during a memory access unit operating cycle period in the first circuit area so as to supply to one of the access ports of the second circuit area the plurality of parallel data serially during the plurality of memory operating cycle periods in synchronization with the second clock signal , and a stretching circuit for receiving data , which the second circuit area has read from the memory array during a read operation cycle period in synchronization with the second clock signal , so as to supply the data to the first circuit area over the read operation cycle period in synchronization with the second clock signal .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (read gate) . 		US5422858A
CLAIM 4 . A semiconductor integrated circuit according to claim 2 , wherein the first circuit area is a spread gate (remote storage device) area whose required function is practically attained on the basis of the form of connecting numerous basic circuits repetitively and wherein the second circuit area is a macro cell whose required function is practically attained by making the integration of circuit elements therein greater than that of those in the spread gate area .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module (write operation) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5422858A
CLAIM 8 . A semiconductor integrated circuit comprising : a first circuit area operating in synchronization with a first clock signal , a second circuit area which is capable of operating in synchronization with a clock signal whose frequency is higher than that of the first clock signal and has a memory array and access ports for writing and reading data simultaneously to and from the memory array , and a rate conversion circuit area for making the second circuit area accessible from the first circuit area , wherein the first circuit area is a spread gate area whose required function is practically attained on the basis of the form of connecting numerous basic circuits repetitively and the second circuit area is a macro cell whose required function is practically attained by making the integration of circuit elements therein greater than that of those in the spread gate area , the rate conversion circuit area further comprises a multiplied clock generator circuit for receiving an access control signal for allowing the first circuit area to gain access to the second circuit area and the first clock signal from the first circuit area , and forming a second clock signal whose frequency is multiplied an optional number of times that of the first clock signal according to the first clock signal and read/write signals for sequentially designating a read operation in synchronization with the second clock signal and the following write operation (storage unit writing module) so as to supply these signals to the second circuit area when the read and write operations are designated in parallel according to the access control signal , a parallel-serial conversion circuit for receiving memory access data for writing and reading in parallel from the first circuit area during a memory access unit operating cycle period in the first circuit area so as to supply to one of the access ports of the second circuit area the plurality of parallel data serially during the plurality of memory operating cycle periods in synchronization with the second clock signal , and a stretching circuit for receiving data , which the second circuit area has read from the memory array during a read operation cycle period in synchronization with the second clock signal , so as to supply the data to the first circuit area over the read operation cycle period in synchronization with the second clock signal .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code (write signal) for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5422858A
CLAIM 8 . A semiconductor integrated circuit comprising : a first circuit area operating in synchronization with a first clock signal , a second circuit area which is capable of operating in synchronization with a clock signal whose frequency is higher than that of the first clock signal and has a memory array and access ports for writing and reading data simultaneously to and from the memory array , and a rate conversion circuit area for making the second circuit area accessible from the first circuit area , wherein the first circuit area is a spread gate area whose required function is practically attained on the basis of the form of connecting numerous basic circuits repetitively and the second circuit area is a macro cell whose required function is practically attained by making the integration of circuit elements therein greater than that of those in the spread gate area , the rate conversion circuit area further comprises a multiplied clock generator circuit for receiving an access control signal for allowing the first circuit area to gain access to the second circuit area and the first clock signal from the first circuit area , and forming a second clock signal whose frequency is multiplied an optional number of times that of the first clock signal according to the first clock signal and read/write signal (program code) s for sequentially designating a read operation in synchronization with the second clock signal and the following write operation so as to supply these signals to the second circuit area when the read and write operations are designated in parallel according to the access control signal , a parallel-serial conversion circuit for receiving memory access data for writing and reading in parallel from the first circuit area during a memory access unit operating cycle period in the first circuit area so as to supply to one of the access ports of the second circuit area the plurality of parallel data serially during the plurality of memory operating cycle periods in synchronization with the second clock signal , and a stretching circuit for receiving data , which the second circuit area has read from the memory array during a read operation cycle period in synchronization with the second clock signal , so as to supply the data to the first circuit area over the read operation cycle period in synchronization with the second clock signal .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5444667A

Filed: 1994-03-31     Issued: 1995-08-22

Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to allow timing generator to latch command signals

(Original Assignee) NEC Corp     (Current Assignee) Renesas Electronics Corp

Takashi Obara
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (first one) of storage units and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (first one) of storage units is stored in a local storage device and the second set (first one) of storage units is stored in a remote storage device . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (first one) contains valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (first one) contain valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first one) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (first one) for which an indication of valid data is stored in the first usage map . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (first one) of storage units with the third set of storage units . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (first one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (first one) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (first one) of private storage units for the server . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (first one) of private storage units and the first usage map of a first server . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (first one) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (first one) contains valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (first one) contain valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (first one) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (first one) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first one) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (first one) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first one) does not contain valid data , reading the data item from the shared storage unit . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (first one) for which an indication of valid data is stored in the first usage map . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (first one) of private storage units with the second set (first one) of private storage units . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (first one) that contain valid data to those corresponding private storage units of the second set (first one) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (first one) of storage units and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (first one) of storage units is stored in a local storage device and the second set (first one) of storage units is stored in a remote storage device . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (first one) contains valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (first one) contain valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first one) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (first one) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (first one) for which an indication of valid data is stored in the first usage map . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (first one) of storage units with the third set of storage units . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (first one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .

US6618736B1
CLAIM 53 . An computer program product (first input) for creating and archiving a file system within at least one storage device comprising a first set (first one) of storage units and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5444667A
CLAIM 1 . A synchronous semiconductor memory device comprising : a) a memory cell array implemented by a plurality of addressable memory cells ;
b) an input and output unit for supplying data bits from and to said memory cell array ;
c) an addressing system responsive to external address signals for selectively coupling said input and output unit with said plurality of addressable memory cells ;
d) a timing generator responsive to external command signals for controlling said input and output unit and said addressing system ;
and e) an input circuit responsive to an external clock signal and an external clock enable signal for producing a main internal control signal , said main internal control signal causing said timing generator to latch said external command signals , said input circuit having e-1) a first input (computer program product) stage assigned to said external clock signal , and enabled with an enable signal , said first input stage being operative to produce an internal clock signal synchronous with said external clock signal , e-2) a second input stage assigned to said external clock enable signal , and enabled with said enable signal , said second input stage being operative to produce an internal clock enable signal synchronous with said external clock enable signal , e-3) a first controller responsive to said internal clock signal for producing a first internal control signal maintained at a first level for a predetermined time period , and e-4) a second controller responsive to said first internal control signal for introducing a time delay between said internal clock enable signal and a second internal control signal , said second internal control signal allowing said first controller to produce said main internal control signal from said internal clock signal maintained at the first level for said predetermined time period .

US5444667A
CLAIM 3 . The synchronous semiconductor memory device as set forth in claim 1 , in which said first controller comprises a first one (first set, second set) -shot pulse generator having a delay circuit for introducing a predetermined time delay into said propagation of said internal clock signal for producing a first delayed internal clock signal and a logic gate supplied with said internal clock signal and said first delayed internal clock signal for producing said first internal control signal , and a second one-shot pulse generator having a delay circuit for introducing said predetermined time delay into propagation of said internal clock signal for producing a second delayed internal clock signal , and a logic gate supplied with said internal clock signal and said second delayed internal clock signal for producing said main internal control signal , said delay circuit of said second one-shot pulse generator having a logic gate being enabled with said second internal control signal .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5430676A

Filed: 1994-02-25     Issued: 1995-07-04

Dynamic random access memory system

(Original Assignee) Rambus Inc     (Current Assignee) Rambus Inc

Frederick A. Ware, John B. Dillon, Richard M. Barth, Billy W. Garrett, Jr., John G. Atwood, Jr., Michael P. Farmwald
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (receiving information) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (receiving information) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (receiving information) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (receiving information) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage (receiving information) map . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (receiving information) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage (receiving information) map of a first server . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (receiving information) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (receiving information) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (receiving information) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (receiving information) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (receiving information) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (receiving information) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set for which an indication of valid data is stored in the first usage (receiving information) map . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (receiving information) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (write operation) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation (storage unit writing module) ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (receiving information) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (receiving information) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (receiving information) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation ;
column amplifiers coupled to the DRAM array for receiving information (first usage) sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module (write operation) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5430676A
CLAIM 1 . A dynamic random access memory (DRAM) system , comprising : a DRAM array accessed according to a row address and a column address , wherein the row address is decoded to select a selected row of the array for a read/write operation (storage unit writing module) ;
column amplifiers coupled to the DRAM array for receiving information sensed from or to be written into the selected row during the read/write operation ;
a dirty flag which , when set , specifies that the information received in the column amplifiers is different from the information stored in the selected row ;
circuitry for indicating a state in which the column amplifiers are left prior to sensing a next selected row in the array such that if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a dirty state , just prior to sensing the next selected row of the array , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a clean state , the information received in the column amplifiers is written into the selected row after the read/write operation to the selected row is complete , and just prior to sensing the next selected row of the array , the column amplifiers are precharged , if the dirty flag is set and the circuitry indicates that the column amplifiers are indicated to be left in a precharged state , the information received in the column amplifiers is written into the selected row and the column amplifiers are precharged after the read/write operation to the selected row is compete , and if the dirty flag is not set and the circuitry indicates that the column amplifiers are indicated to be placed in a precharged state , the column amplifiers are precharged after the read/write operation to the selected row is complete , wherein at completion of an access to the selected row , the column amplifiers can be left in the dirty state , the clean state , or the precharged state .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5404338A

Filed: 1994-01-31     Issued: 1995-04-04

Synchronous type semiconductor memory device operating in synchronization with an external clock signal

(Original Assignee) Mitsubishi Electric Engineering Co Ltd; Mitsubishi Electric Corp     (Current Assignee) Mitsubishi Electric Corp

Yasumitsu Murai, Hisashi Iwamoto, Yasuhiro Konishi, Naoya Watanabe, Seiji Sawada
US6618736B1
CLAIM 1 . A method for file system (read data bus) creation (read data bus) and archival comprising : providing a first set (second connecting means, selected word line) of storage units and a second set of storage units , each storage unit (counter means, row direction) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US5404338A
CLAIM 64 . The device according to claim 56 , further including , a data output terminal , a read data bus (file system creation, file system) for transferring data from the selected memory cells , read latch means for receiving data from said read data bus for output to said data output terminal , transfer means for transferring data from said read data bus to said read latch means , and bus drive means for driving said read data bus to the predetermined potential when said transfer data from said read data bus to said read latch means .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (second connecting means, selected word line) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (instruction signal) . 		US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 16 . The device according to clam 12 , wherein each of said plurality of data registers includes , a preamplifier for amplifying a data signal from a selected memory cell , a master latch for latching the data signal from said preamplifier , transfer gate responsive to a transfer instruction signal (remote storage device) generated after activation of said preamplifier , for transferring the latched data signal of said master latch , and a slave latch for latching the data signal transferred from said transfer gate .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (counter means, row direction) of the second set contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (counter means, row direction) of the first set (second connecting means, selected word line) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (counter means, row direction) of the first set (second connecting means, selected word line) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (counter means, row direction) of the third set corresponding to one of the storage units of the first set (second connecting means, selected word line) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (counter means, row direction) of the third set contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (counter means, row direction) of the first set (second connecting means, selected word line) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (counter means, row direction) of the first set (second connecting means, selected word line) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (counter means, row direction) of the first set (second connecting means, selected word line) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (counter means, row direction) of the second set for which an indication of valid data is stored in the first usage map . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (counter means, row direction) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (determined order) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (second connecting means, selected word line) of private storage units , each of the private storage units corresponding to a shared storage unit (counter means, row direction) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 35 . A synchronous type semiconductor memory device taking in an external signal and input data in synchronization with a clock of a series of pulses and having a plurality of memory cells selected simultaneously in a memory array including a multiplicity of memory cells arranged in rows and columns , comprising : a data input terminal for receiving said input data ;
a plurality of data registers provided receiving data from said data input terminal , for storing data to be written into the plurality of memory cells simultaneously selected ;
register selection means responsive to a column selection instructing signal applied in synchronization with said clock for sequentially selecting said data registers in a predetermined order (file systems, program code) to couple a selected data register to said data input terminal ;
and transfer means responsive to said column selection designating signal for transferring data in said data registers to corresponding memory cells on a unit of a predetermined number of data registers .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (read data bus) of each server comprises a combination of the set of shared storage units and the first set (second connecting means, selected word line) of private storage units for the server . 		US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 64 . The device according to claim 56 , further including , a data output terminal , a read data bus (file system creation, file system) for transferring data from the selected memory cells , read latch means for receiving data from said read data bus for output to said data output terminal , transfer means for transferring data from said read data bus to said read latch means , and bus drive means for driving said read data bus to the predetermined potential when said transfer data from said read data bus to said read latch means .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (second connecting means, selected word line) of private storage units and the first usage map of a first server . 		US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (read data bus) for a second server using the stored template . 		US5404338A
CLAIM 64 . The device according to claim 56 , further including , a data output terminal , a read data bus (file system creation, file system) for transferring data from the selected memory cells , read latch means for receiving data from said read data bus for output to said data output terminal , transfer means for transferring data from said read data bus to said read latch means , and bus drive means for driving said read data bus to the predetermined potential when said transfer data from said read data bus to said read latch means .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (instruction signal) . 		US5404338A
CLAIM 16 . The device according to clam 12 , wherein each of said plurality of data registers includes , a preamplifier for amplifying a data signal from a selected memory cell , a master latch for latching the data signal from said preamplifier , transfer gate responsive to a transfer instruction signal (remote storage device) generated after activation of said preamplifier , for transferring the latched data signal of said master latch , and a slave latch for latching the data signal transferred from said transfer gate .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (counter means, row direction) contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (counter means, row direction) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (counter means, row direction) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (counter means, row direction) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (counter means, row direction) of the second set contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (counter means, row direction) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (counter means, row direction) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (second connecting means, selected word line) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (counter means, row direction) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (second connecting means, selected word line) does not contain valid data , reading the data item from the shared storage unit . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (counter means, row direction) of the first set (second connecting means, selected word line) for which an indication of valid data is stored in the first usage map . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (second connecting means, selected word line) of private storage units with the second set of private storage units . 		US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (second connecting means, selected word line) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (counter means, row direction) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (read data bus) within at least one storage device comprising a first set (second connecting means, selected word line) of storage units and a second set of storage units , each storage unit (counter means, row direction) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US5404338A
CLAIM 64 . The device according to claim 56 , further including , a data output terminal , a read data bus (file system creation, file system) for transferring data from the selected memory cells , read latch means for receiving data from said read data bus for output to said data output terminal , transfer means for transferring data from said read data bus to said read latch means , and bus drive means for driving said read data bus to the predetermined potential when said transfer data from said read data bus to said read latch means .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (second connecting means, selected word line) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (instruction signal) . 		US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 16 . The device according to clam 12 , wherein each of said plurality of data registers includes , a preamplifier for amplifying a data signal from a selected memory cell , a master latch for latching the data signal from said preamplifier , transfer gate responsive to a transfer instruction signal (remote storage device) generated after activation of said preamplifier , for transferring the latched data signal of said master latch , and a slave latch for latching the data signal transferred from said transfer gate .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (counter means, row direction) of the second set contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (counter means, row direction) of the first set (second connecting means, selected word line) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (counter means, row direction) of the first set (second connecting means, selected word line) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (counter means, row direction) of the third set corresponding to one of the storage units of the first set (second connecting means, selected word line) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (counter means, row direction) of the first set (second connecting means, selected word line) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (counter means, row direction) of the third set contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (counter means, row direction) of the first set (second connecting means, selected word line) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (counter means, row direction) of the first set (second connecting means, selected word line) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (counter means, row direction) of the first set (second connecting means, selected word line) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (counter means, row direction) of the second set for which an indication of valid data is stored in the first usage map . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (counter means, row direction) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (read data bus) within at least one storage device comprising a first set (second connecting means, selected word line) of storage units and a second set of storage units , each storage unit (counter means, row direction) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code (determined order) for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5404338A
CLAIM 8 . The device according to claim 4 , wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction (storage unit, storage unit update module) .

US5404338A
CLAIM 9 . A semiconductor memory device , comprising : a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns , and grouped into a first group of blocks and a second group of blocks ;
a plurality of sense amplifiers provided , on both sides of respective memory array blocks , corresponding to said columns , one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column ;
a plurality of local IO lines arranged corresponding to said plurality of memory array blocks ;
a first global line ;
a second global IO line ;
and connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines ;
said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line ;
(b) second connecting means (first set) provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line ;
(c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line ;
and (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line .

US5404338A
CLAIM 35 . A synchronous type semiconductor memory device taking in an external signal and input data in synchronization with a clock of a series of pulses and having a plurality of memory cells selected simultaneously in a memory array including a multiplicity of memory cells arranged in rows and columns , comprising : a data input terminal for receiving said input data ;
a plurality of data registers provided receiving data from said data input terminal , for storing data to be written into the plurality of memory cells simultaneously selected ;
register selection means responsive to a column selection instructing signal applied in synchronization with said clock for sequentially selecting said data registers in a predetermined order (file systems, program code) to couple a selected data register to said data input terminal ;
and transfer means responsive to said column selection designating signal for transferring data in said data registers to corresponding memory cells on a unit of a predetermined number of data registers .

US5404338A
CLAIM 46 . The device according to claim 44 , further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells , and wherein said reference voltage is supplied to a selected word line (first set) as a boosted word line drive signal .

US5404338A
CLAIM 57 . The device according to claim 56 , wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively , and counter means (storage unit, storage unit update module) responsive to said data write designation signal for counting said clock signal , and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal .

US5404338A
CLAIM 64 . The device according to claim 56 , further including , a data output terminal , a read data bus (file system creation, file system) for transferring data from the selected memory cells , read latch means for receiving data from said read data bus for output to said data output terminal , transfer means for transferring data from said read data bus to said read latch means , and bus drive means for driving said read data bus to the predetermined potential when said transfer data from said read data bus to said read latch means .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5390149A

Filed: 1994-01-21     Issued: 1995-02-14

System including a data processor, a synchronous dram, a peripheral device, and a system clock

(Original Assignee) Texas Instruments Inc     (Current Assignee) Texas Instruments Inc

Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le, Joseph H. Neal, Kenneth A. Poteet, Joseph P. Hartigan, Roger D. Norwood
US6618736B1
CLAIM 1 . A method for file system creation (d line) and archival comprising : providing a first set of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US5390149A
CLAIM 68 . A method for reading data bits from a memory device having a data output terminal , the method comprising the steps of : receiving a system clock signal ;
activating a row address enabling signal for activating a first word line (file system creation) of an array in synchronism with the system clock signal ;
applying a first column address to the array for selecting a first plurality of data bits ;
deactivating the row address enabling signal ;
activating the row address enabling signal for activating a second word line of the array in synchronism with the system clock signal ;
applying a second column address to the array for selecting a second plurality of data bits ;
and sequentially transmitting the data bits of the first and second pluralities of data bits to the data output terminal in synchronism with the system clock signal , at least one data bit being transmitted to the output terminal per system clock cycle while the first and second pluralities of data bits are being transmitted .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set (second set) of storage units is stored in a remote storage device . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (second set) contains valid data . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (second set) contain valid data . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (second set) of storage units with the third set of storage units . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (second set) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (second set) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (second set) contains valid data . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (second set) contain valid data . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units with the second set (second set) of private storage units . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set (second set) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set (second set) of storage units is stored in a remote storage device . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (second set) contains valid data . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (second set) contain valid data . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (second set) of storage units with the third set of storage units . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (second set) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5390149A
CLAIM 31 . A method for accessing a synchronous random access memory , in accordance with claim 27 , comprising the further steps of : thereafter addressing another row of storage cells in the array of storage cells ;
applying a second initial column address to the column address counter ;
reading another selected data bit out of the another addressed row of the array by accessing a second set (second set) of columns of storage cells in the array ;
and transmitting a data bit from another selected storage cell through the output to a data bus in synchronism with the system clock signal .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5530623A

Filed: 1993-11-19     Issued: 1996-06-25

High speed memory packaging scheme

(Original Assignee) NCR Corp     (Current Assignee) Intellectual Ventures I LLC

Ikuo J. Sanwo, Michael A. Hoffman, Hyung S. Kim
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (respective point, more memory, first one) of storage units and a second set (respective point, more memory, first one) of storage units , each storage unit (two rows) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets (common set) of storage units are stored in a same storage device . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set (second sets) of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (respective point, more memory, first one) of storage units is stored in a local storage device and the second set (respective point, more memory, first one) of storage units is stored in a remote storage device . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (two rows) of the second set (respective point, more memory, first one) contains valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (respective point, more memory, first one) contain valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (two rows) of the first set (respective point, more memory, first one) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (respective point, more memory, first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (two rows) of the first set (respective point, more memory, first one) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (respective point, more memory, first one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (respective point, more memory, first one) of storage units , each storage unit (two rows) of the third set corresponding to one of the storage units of the first set (respective point, more memory, first one) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (two rows) of the third set (respective point, more memory, first one) contains valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (respective point, more memory, first one) contain valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (two rows) of the first set (respective point, more memory, first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (respective point, more memory, first one) contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (two rows) of the first set (respective point, more memory, first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (respective point, more memory, first one) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (respective point, more memory, first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (two rows) of the first set (respective point, more memory, first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (respective point, more memory, first one) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (respective point, more memory, first one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (two rows) of the second set (respective point, more memory, first one) for which an indication of valid data is stored in the first usage map . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (respective point, more memory, first one) of storage units with the third set (respective point, more memory, first one) of storage units . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (respective point, more memory, first one) that contain valid data to those corresponding storage units of the third set (respective point, more memory, first one) that do not contain valid data ;

and for each storage unit (two rows) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (respective point, more memory, first one) of private storage units , each of the private storage units corresponding to a shared storage unit (two rows) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (respective point, more memory, first one) of private storage units for the server . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (respective point, more memory, first one) of private storage units and the first usage map of a first server . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (two rows) contains valid data . 		US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (two rows) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (two rows) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (respective point, more memory, first one) of private storage units , each private storage unit (two rows) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (two rows) of the second set (respective point, more memory, first one) contains valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (respective point, more memory, first one) contain valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (two rows) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (respective point, more memory, first one) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (two rows) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (respective point, more memory, first one) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (respective point, more memory, first one) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (two rows) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (respective point, more memory, first one) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (respective point, more memory, first one) does not contain valid data , reading the data item from the shared storage unit . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (two rows) of the first set (respective point, more memory, first one) for which an indication of valid data is stored in the first usage map . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (respective point, more memory, first one) of private storage units with the second set (respective point, more memory, first one) of private storage units . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (respective point, more memory, first one) that contain valid data to those corresponding private storage units of the second set (respective point, more memory, first one) that do not contain valid data ;

and for each private storage unit (two rows) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (respective point, more memory, first one) of storage units and a second set (respective point, more memory, first one) of storage units , each storage unit (two rows) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets (common set) of storage units are stored in a same storage device . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set (second sets) of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (respective point, more memory, first one) of storage units is stored in a local storage device and the second set (respective point, more memory, first one) of storage units is stored in a remote storage device . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (two rows) of the second set (respective point, more memory, first one) contains valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (respective point, more memory, first one) contain valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (two rows) of the first set (respective point, more memory, first one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (respective point, more memory, first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (two rows) of the first set (respective point, more memory, first one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (respective point, more memory, first one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set (respective point, more memory, first one) of storage units , each storage unit (two rows) of the third set corresponding to one of the storage units of the first set (respective point, more memory, first one) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (two rows) of the first set (respective point, more memory, first one) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set (respective point, more memory, first one) ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (two rows) of the third set (respective point, more memory, first one) contains valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units of the third set (respective point, more memory, first one) contain valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (two rows) of the first set (respective point, more memory, first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (respective point, more memory, first one) contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (two rows) of the first set (respective point, more memory, first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (respective point, more memory, first one) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (respective point, more memory, first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (two rows) of the first set (respective point, more memory, first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set (respective point, more memory, first one) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (respective point, more memory, first one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (two rows) of the second set (respective point, more memory, first one) for which an indication of valid data is stored in the first usage map . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (respective point, more memory, first one) of storage units with the third set (respective point, more memory, first one) of storage units . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (respective point, more memory, first one) that contain valid data to those corresponding storage units of the third set (respective point, more memory, first one) that do not contain valid data ;

and wherein the storage unit (two rows) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (respective point, more memory, first one) of storage units and a second set (respective point, more memory, first one) of storage units , each storage unit (two rows) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5530623A
CLAIM 1 . A computer memory system , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective point (first set, third set, second set) s on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
and a plurality of memory modules for coupling with said plurality of connectors ;
each one of said connectors providing electrical connection between said plurality of transmission lines and memory logic within a memory module coupled with said connector , and providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .

US5530623A
CLAIM 2 . The computer memory system according to claim 1 , wherein : each one of said connectors comprises an electrical edge connector including a plurality of signal contacts arranged in pairs forming two rows (storage unit) , a first row being comprised of a first member from each of said pairs and a second row comprised of a second member from each of said pairs , and each one of said transmission lines comprises a plurality of transmission line segments connected between said connectors , each segment providing electrical connection between a first member of a pair of signal contacts associated with a first one (first set, third set, second set) of said connectors and a second member of a pair of signal contacts associated with a second one of said connectors .

US5530623A
CLAIM 10 . A computer memory system for receiving one or more memory (first set, third set, second set) modules , comprising : a circuit board ;
a plurality of connectors mounted to said circuit board ;
a common set of transmission lines within said circuit board for the transmission of address , data and control signals to and from said plurality of connectors , each of said transmission lines sequentially connecting respective points on said plurality of connectors , whereby said plurality of connectors are connected in the same sequence by each of said transmission lines ;
each one of said connectors for receiving one of said memory modules and providing electrical connection between said plurality of transmission lines and memory logic within said memory module coupled with said connector ;
and each one of said connectors providing an open circuit in each of said transmission lines in the absence of a memory module coupled with said connector , and including means for closing the open circuits for each one of said transmission lines at said connector when one of said memory modules is coupled with said connector ;
whereby each one of said transmission lines has a connected length determined by the number of memory modules installed within consecutive connectors , eliminating undesirable transmission line effects resulting from greater transmission line lengths .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5495607A

Filed: 1993-11-15     Issued: 1996-02-27

Network management system having virtual catalog overview of files distributively stored across network domain

(Original Assignee) Seagate Peripherals Inc     (Current Assignee) Clouding Corp

Thomas Pisello, David Crossmier, Paul Ashton
US6618736B1
CLAIM 1 . A method for file system (stored files, data files) creation and archival comprising : providing a first set of storage units (nonvolatile data storage device) and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files (file systems, file system) , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US5495607A
CLAIM 21 . A network system according to claim 20 wherein the DAS further includes a second virtual catalog containing copies of file identifying information previously stored in the local catalogs of said plurality of file-servers at a first time substantially earlier than that of the currently-stored files (file systems, file system) .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (nonvolatile data storage device) are stored in a same storage device . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units (nonvolatile data storage device) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (nonvolatile data storage device) of the second set contain valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (nonvolatile data storage device) , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (nonvolatile data storage device) of the third set contain valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units (nonvolatile data storage device) with the third set of storage units . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (nonvolatile data storage device) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (stored files, data files) of a plurality of servers , the method comprising : providing a set of shared storage units (nonvolatile data storage device) ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files (file systems, file system) , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US5495607A
CLAIM 21 . A network system according to claim 20 wherein the DAS further includes a second virtual catalog containing copies of file identifying information previously stored in the local catalogs of said plurality of file-servers at a first time substantially earlier than that of the currently-stored files (file systems, file system) .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system (stored files, data files) of each server comprises a combination of the set of shared storage units (nonvolatile data storage device) and the first set of private storage units for the server . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files (file systems, file system) , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US5495607A
CLAIM 21 . A network system according to claim 20 wherein the DAS further includes a second virtual catalog containing copies of file identifying information previously stored in the local catalogs of said plurality of file-servers at a first time substantially earlier than that of the currently-stored files (file systems, file system) .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units (nonvolatile data storage device) and the first usage map of a first server . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system (stored files, data files) for a second server using the stored template . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device storing a plurality of data files (file systems, file system) , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US5495607A
CLAIM 21 . A network system according to claim 20 wherein the DAS further includes a second virtual catalog containing copies of file identifying information previously stored in the local catalogs of said plurality of file-servers at a first time substantially earlier than that of the currently-stored files (file systems, file system) .

US6618736B1
CLAIM 21 . The method of claim 17 , wherein the shared and private storage units (nonvolatile data storage device) are stored in a same storage device . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units (nonvolatile data storage device) are stored a local storage device and the private storage units are stored in a remote storage device . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the private storage units (nonvolatile data storage device) contain valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units (nonvolatile data storage device) , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (nonvolatile data storage device) of the second set contain valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units (nonvolatile data storage device) with the second set of private storage units . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (nonvolatile data storage device) of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system (stored files, data files) within at least one storage device comprising a first set of storage units (nonvolatile data storage device) and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files (file systems, file system) , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US5495607A
CLAIM 21 . A network system according to claim 20 wherein the DAS further includes a second virtual catalog containing copies of file identifying information previously stored in the local catalogs of said plurality of file-servers at a first time substantially earlier than that of the currently-stored files (file systems, file system) .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets of storage units (nonvolatile data storage device) are stored in a same storage device . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units (nonvolatile data storage device) is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (nonvolatile data storage device) of the second set contain valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (nonvolatile data storage device) , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map is initially reset to indicate that none of the storage units (nonvolatile data storage device) of the third set contain valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set of storage units (nonvolatile data storage device) with the third set of storage units . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (nonvolatile data storage device) of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (stored files, data files) within at least one storage device comprising a first set of storage units (nonvolatile data storage device) and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code (checking means) for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5495607A
CLAIM 1 . A network system comprising : (a) a network-linking backbone ;
(b) a plurality of file-servers operatively coupled to the backbone for providing file-serving services over the backbone , each file server having a nonvolatile data storage device (storage units) storing a plurality of data files (file systems, file system) , the respective data storage device of each file server further having a local catalog stored within said respective data storage device for identifying each file of the respective data storage device by name and storage location ;
and (c) a domain administrating server (DAS) operatively coupled to the backbone , wherein the DAS has a domain-wide virtual catalog containing copies of the file identifying information currently stored in the local catalogs of said plurality of file-servers , wherein the DAS has oversight means for overseeing and managing domain-wide activities including a transfer of file data from a first of the file servers to a second of the file servers , and wherein the oversight means consults the domain-wide virtual catalog to identify the location of a source file in said first file server from which said to-be-transferred file data is to be obtained .

US5495607A
CLAIM 14 . A network system according to claim 9 wherein said operations supporting infrastructure of each file-server includes local data path integrity checking means (program code) for assuring proper interconnections between two or more local components within the respective file-server .

US5495607A
CLAIM 21 . A network system according to claim 20 wherein the DAS further includes a second virtual catalog containing copies of file identifying information previously stored in the local catalogs of said plurality of file-servers at a first time substantially earlier than that of the currently-stored files (file systems, file system) .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5504873A

Filed: 1993-11-12     Issued: 1996-04-02

Mass data storage and retrieval system

(Original Assignee) E Systems Inc     (Current Assignee) Raytheon Co

Charles W. Martin, Fredrick S. Reid, Gary L. Forbus, Steve M. Adams, C. Patrick Shannon, Eric A. Pirpich
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set (second command) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set (second command) of storage units is stored in a remote storage device (read information) . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US5504873A
CLAIM 6 . The system as in claim 5 wherein the buffer means includes read-after-write comparison means for comparing the stored read information (remote storage device) with the stored written information to verify the accuracy of the recording .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (second command) contains valid data . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (second command) contain valid data . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second command) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second command) does not contain valid data , reading the data item from the storage unit of the first set . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second command) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second command) does not contain valid data , reading the data item from the storage unit of the first set . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (second command) for which an indication of valid data is stored in the first usage map . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (second command) of storage units with the third set of storage units . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (second command) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (enable access) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5504873A
CLAIM 9 . The system as in claim 8 wherein the means for enabling comprises means for positioning each storage module to enable access (file systems) by said accessor to each side of the storage module .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system for a second server (second access) using the stored template . 		US5504873A
CLAIM 15 . A mass data storage system comprising : a storage module for storing a plurality of discrete data storage elements , the storage module having first and second opposed sides , the first side having a first means for providing access to one of the plurality of data storage elements and the second side having second means for providing access to the one of the plurality of data storage elements ;
a first accessor module for retrieving and carrying one of the plurality of data storage elements through the first means for providing access to a first recorder module ;
a second access (second server) or module for retrieving and carrying one of the plurality of data storage elements from the second means for providing access to a second record module ;
and first and second recorder modules each having means for receiving one of the plurality of data elements and means for writing data to and reading data from the one of the plurality of data storage elements .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (read information) . 		US5504873A
CLAIM 6 . The system as in claim 5 wherein the buffer means includes read-after-write comparison means for comparing the stored read information (remote storage device) with the stored written information to verify the accuracy of the recording .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (second command) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (second command) contains valid data . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (second command) contain valid data . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second command) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second command) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second command) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units with the second set (second command) of private storage units . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set (second command) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (second command) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set (second command) of storage units is stored in a remote storage device (read information) . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US5504873A
CLAIM 6 . The system as in claim 5 wherein the buffer means includes read-after-write comparison means for comparing the stored read information (remote storage device) with the stored written information to verify the accuracy of the recording .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (second command) contains valid data . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (second command) contain valid data . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second command) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second command) does not contain valid data , to read the data item from the storage unit of the first set . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second command) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second command) does not contain valid data , to read the data item from the storage unit of the first set . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (second command) for which an indication of valid data is stored in the first usage map . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (second command) of storage units with the third set of storage units . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (second command) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (second command) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5504873A
CLAIM 1 . A mass data storage and retrieval system , comprising : a plurality of information storage means forming a mass storage library ;
a plurality of data recorder modules for reading information from and writing information to information storage means , each of said data recorder modules configured to accept loading of at least one of the plurality of information storage means ;
interface means for bi-directionally coupling the data recorder modules to a host computer for simultaneous reading and writing of information from and to one of the plurality of information storage means loaded into one of the plurality of data recorder modules ;
and a control computer for generating a first command signal output to the mass storage library for loading one of the plurality of information storage means in one of the plurality of data recorder modules and for generating a second command (second set) signal for coupling the interface means to the data recorder module loaded with the information storage means .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5386375A

Filed: 1993-11-01     Issued: 1995-01-31

Floating point data processor and a method for performing a floating point square root operation within the data processor

(Original Assignee) Motorola Solutions Inc     (Current Assignee) Motorola Solutions Inc

Roger A. Smith
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set (value v) of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value v (third set) ia the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set (value v) contains valid data . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value v (third set) ia the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units of the third set (value v) contain valid data . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value v (third set) ia the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (value v) contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value v (third set) ia the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (value v) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value v (third set) ia the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set (value v) does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value v (third set) ia the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set of storage units with the third set (value v) of storage units . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value v (third set) ia the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set (value v) that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value v (third set) ia the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5386375A
CLAIM 21 . A method for performing a floating point operation within a data processing system , the data processing system having a central processing unit , a storage device (data item) , and circuitry for processing floating point operations , the method comprising : transmitting a number having an exact mathematical square root from the storage device to the central processing unit via a data bus , the number having a floating point representation within the data processing system ;
determining , by a decoding process in the central processing unit , that the data processing system is requesting that the square root of the number be calculated ;
transmitting the number from the central processing unit to the circuitry for processing floating point operations ;
generating and storing an approximate inverse square root of the number within the circuitry for processing floating point operations wherein the approximate inverse square root has more than P/2 bits of precision where P is a finite integer greater than zero and equals the number of significant bits in the floating point representation ;
providing an exact component value via the circuitry for processing floating point operations , the exact component value being generated from the number and the approximate inverse square root wherein the exact component value has a precise representation in the floating point representation ;
providing , via the circuitry for processing floating point operations , a small component value generated from the number and the approximate inverse square root wherein the small component value is significantly less than the exact component value , the sum of the exact component value and the small component value differs from the exact mathematical square root by less than one half of a value of a least significant bit position of the sum ;
generating a trial value using the circuitry for processing floating point operations , the trial value is generated by adding the exact component value to the small component value wherein the trial value is altered to be representable in P bits ;
and selecting either the trial value or the trial value plus a constant as the square root of the number and providing the square root of the number within the data processing system .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set (value v) that do not contain valid data ;

and wherein the storage unit update module (positive integer) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5386375A
CLAIM 30 . The method of claim 21 wherein the step of providing an exact component value comprises : calculating a first value (s) having having a number k of significant bits wherein k is a positive integer (storage unit update module) less than P and small enough to calculate the exact component value without rounding error , the first value (s) being said number having an exact mathematical square root altered to include only k significant bits ;
and using the first value (s) to calculate the exact component without rounding error .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5428389A

Filed: 1993-08-12     Issued: 1995-06-27

Image data storage/processing apparatus

(Original Assignee) Fuji Photo Film Co Ltd     (Current Assignee) Fujifilm Corp

Kenji Ito, Kaoru Adachi, Osamu Saito
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit (processing apparatus) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (processing apparatus) of the second set contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (processing apparatus) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (processing apparatus) of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (processing apparatus) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (processing apparatus) of the third set contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (processing apparatus) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (processing apparatus) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (processing apparatus) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (processing apparatus) of the second set for which an indication of valid data is stored in the first usage map . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (processing apparatus) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (processing apparatus) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage map of a first server (first pixel) . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixel (first server) s , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (processing apparatus) contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (processing apparatus) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (processing apparatus) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (processing apparatus) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (processing apparatus) of the second set contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (processing apparatus) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (processing apparatus) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (processing apparatus) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (processing apparatus) of the first set for which an indication of valid data is stored in the first usage map . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (processing apparatus) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (processing apparatus) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (processing apparatus) of the second set contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (processing apparatus) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (processing apparatus) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (processing apparatus) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (processing apparatus) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (processing apparatus) of the third set contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (processing apparatus) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (processing apparatus) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (processing apparatus) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (processing apparatus) of the second set for which an indication of valid data is stored in the first usage map . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (processing apparatus) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (processing apparatus) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5428389A
CLAIM 1 . An image data storage apparatus applicable to an image processing apparatus (storage unit) adopting a compression scheme according to an orthogonal transformation , said image data storage apparatus comprising : first storage means for storing first image data in a form of units of blocks corresponding to first pixels , covering a first group of even-numbered pixel lines constituting an image ;
second storage means for storing second image data in a form of units of blocks corresponding to second pixels covering a second group of odd-numbered pixel lines each interlacing said first group of even-numbered pixel lines ;
control means for controlling a readout timing of said first and second image data respectively stored in said first and second storage means so that said first and second image data are simultaneously read out and continuously aligned ;
image processing means for processing said first and second image data received from said first and second storage means in a form of units of blocks ;
wherein said control means provides such a control that said first and second image data are simultaneously read out from said first and second storage means , and either of the first and second image data is read out with delay by the time required for reading out each one of them so that said first and second image data are continuously aligned .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5329484A

Filed: 1993-06-02     Issued: 1994-07-12

Semiconductor memory circuit, semiconductor memory module using the same, and acoustic signal reproducing system

(Original Assignee) NEC Corp     (Current Assignee) NEC Corp

Hideo Tsuiki
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (first one) of storage units and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (first one) of storage units is stored in a local storage device and the second set (first one) of storage units is stored in a remote storage device . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (first one) contains valid data . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (first one) contain valid data . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first one) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (first one) for which an indication of valid data is stored in the first usage map . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (first one) of storage units with the third set of storage units . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (first one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (first one) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (first one) of private storage units for the server . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (first one) of private storage units and the first usage map of a first server . 		US5329484A
CLAIM 12 . An acoustic signal reproducing system including : means for generating a synchronous signal ;
means receiving data from an external for generating a digital code of a predetermined length ;
means receiving said digital code for converting said received digital code into an analog signal ;
a plurality of semiconductor memory modules connected to each other in a cascaded manner , each of said semiconductor memory modules comprising : a substantially square package accommodating therein a semiconductor memory circuit which includes a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been completed , a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external ;
a set of terminals formed on each of four sides of said square package , the terminals on the four sides being so configured that the same kink of signal is transferred through positionally corresponding terminals of four sides of the square package , the terminals on one side being of a plug type and the terminals on the remaining three sides being of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines , positionally corresponding socket type terminals of said three sides being interconnected so as to interconnecting the terminals for the same signal , a first one (first set, second set) of said cascaded semiconductor memory modules being connected to supply said data to said digital code generating means , a tail end one of said cascaded semiconductor memory modules being connected with a terminator .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module (two data) configured , in response to the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5329484A
CLAIM 1 . A semiconductor memory circuit comprising a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been complete a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data (storage unit reading module, storage unit update module) , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module (two data) configured , in response to the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5329484A
CLAIM 1 . A semiconductor memory circuit comprising a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been complete a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data (storage unit reading module, storage unit update module) , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module (two data) configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5329484A
CLAIM 1 . A semiconductor memory circuit comprising a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been complete a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data (storage unit reading module, storage unit update module) , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module (two data) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5329484A
CLAIM 1 . A semiconductor memory circuit comprising a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been complete a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data (storage unit reading module, storage unit update module) , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module (two data) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5329484A
CLAIM 1 . A semiconductor memory circuit comprising a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been complete a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data (storage unit reading module, storage unit update module) , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (first one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (two data) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5329484A
CLAIM 1 . A semiconductor memory circuit comprising a semiconductor memory device , a read-out controller generating on the basis of a synchronous signal supplied from an external an address signal to said semiconductor memory device for the purpose of reading out data from said semiconductor memory device , said read-out controller also generating a read end signal when the reading of the data from said read-out controller has been complete a feed-out means receiving the data read out from said semiconductor memory device for outputting the received data , a first gate means receiving the data outputted from said feed-out means and data from an external for outputting a selected one of the received two data (storage unit reading module, storage unit update module) , a feed-out control means receiving said read end signal for generating a feed-out control signal , a second gate means responding to said feed-out control signal to control said read-out control means so as to stop the generation of said address signal supplied to said semiconductor memory device , and a third gate means responding to said feed-out control signal to start to supply said synchronous signal to an external .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5392239A

Filed: 1993-05-06     Issued: 1995-02-21

Burst-mode DRAM

(Original Assignee) S3 Inc     (Current Assignee) Samsung Electronics Co Ltd

Neal D. Margulis, Takatoshi Ishii
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set (second set) of storage units is stored in a remote storage device . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (second set) contains valid data . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (second set) contain valid data . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (second set) of storage units with the third set of storage units . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (second set) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (second set) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (second set) contains valid data . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (second set) contain valid data . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set of private storage units with the second set (second set) of private storage units . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set (second set) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (memory circuit) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US5392239A
CLAIM 7 . In a memory circuit (storage unit writing module) , a burst mode controller comprising : a signal detector for concurrently detecting a burst enable signal and a row address strobe signal (RAS) to define a burst mode ;
and means for incrementing an accessed column address when a column address strobe CAS signal is applied during the burst mode .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set (second set) of storage units is stored in a remote storage device . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (second set) contains valid data . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (second set) contain valid data . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module (memory circuit) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5392239A
CLAIM 7 . In a memory circuit (storage unit writing module) , a burst mode controller comprising : a signal detector for concurrently detecting a burst enable signal and a row address strobe signal (RAS) to define a burst mode ;
and means for incrementing an accessed column address when a column address strobe CAS signal is applied during the burst mode .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (second set) of storage units with the third set of storage units . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (second set) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .

US6618736B1
CLAIM 53 . An computer program product (digital storage) for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5392239A
CLAIM 4 . A method for accessing a storage device , said storage device comprising an asynchronously-accessible dynamic random access memory (DRAM) circuit having a matrix of digital storage (computer program product) locations arranged in rows and columns , the method comprising the steps of : receiving a first address along a set of address lines ;
receiving a second address along the address lines ;
generating at least one burst address based on the second address ;
applying the burst address to the storage device along a second set (second set) of address lines instead of the address lines ;
and accessing a storage location within the storage device indicated by the first address and the burst address .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5544347A

Filed: 1993-04-23     Issued: 1996-08-06

Data storage system controlled remote data mirroring with respectively maintained data indices

(Original Assignee) EMC Corp     (Current Assignee) EMC Corp

Moshe Yanai, Natan Vishlitzky, Bruno Alterescu, Daniel Castel, Gadi Shklarsky
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (first location) . 		US5544347A
CLAIM 1 . A system for automatically providing and maintaining data , said system comprising : a host computer located in a first geographic location ;
a first data storage system located in a first geographic location and coupled to said host computer , for storing data to be accessed by at least said host computer ;
a second data storage system located in a second geographic location geographically remote from said first location (remote storage device) , coupled to said first data storage system , for receiving at least data from said first data storage system ;
and said first data storage system enabling transfer of said data to said second data storage system , concurrently with said data received from said host computer , so as to nearly simultaneously maintain a concurrent copy of data stored on said first data storage system and on said second data storage system wherein both said first and said second data storage systems maintain an index , said index including at least a first indicator providing an indication of whether a predetermined data element stored on said first data storage system is valid , and at least a second indicator providing an indication of whether said predetermined data element stored on said second data storage system is valid .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (secondary data) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5544347A
CLAIM 3 . The system of claim 1 , wherein said second data storage system provides an acknowledgment after said data has been received and stored on said secondary data (archiving file systems) storage system .

US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (first location) . 		US5544347A
CLAIM 1 . A system for automatically providing and maintaining data , said system comprising : a host computer located in a first geographic location ;
a first data storage system located in a first geographic location and coupled to said host computer , for storing data to be accessed by at least said host computer ;
a second data storage system located in a second geographic location geographically remote from said first location (remote storage device) , coupled to said first data storage system , for receiving at least data from said first data storage system ;
and said first data storage system enabling transfer of said data to said second data storage system , concurrently with said data received from said host computer , so as to nearly simultaneously maintain a concurrent copy of data stored on said first data storage system and on said second data storage system wherein both said first and said second data storage systems maintain an index , said index including at least a first indicator providing an indication of whether a predetermined data element stored on said first data storage system is valid , and at least a second indicator providing an indication of whether said predetermined data element stored on said second data storage system is valid .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (first location) . 		US5544347A
CLAIM 1 . A system for automatically providing and maintaining data , said system comprising : a host computer located in a first geographic location ;
a first data storage system located in a first geographic location and coupled to said host computer , for storing data to be accessed by at least said host computer ;
a second data storage system located in a second geographic location geographically remote from said first location (remote storage device) , coupled to said first data storage system , for receiving at least data from said first data storage system ;
and said first data storage system enabling transfer of said data to said second data storage system , concurrently with said data received from said host computer , so as to nearly simultaneously maintain a concurrent copy of data stored on said first data storage system and on said second data storage system wherein both said first and said second data storage systems maintain an index , said index including at least a first indicator providing an indication of whether a predetermined data element stored on said first data storage system is valid , and at least a second indicator providing an indication of whether said predetermined data element stored on said second data storage system is valid .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5544347A
CLAIM 8 . The system of claim 5 , wherein said maintained index includes at least a list of data which must be copied from said first data storage storage to said second storage system and , a list of data storage device (data item) storage locations for which a format command is pending and for which an invalid track exists .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5384745A

Filed: 1993-04-14     Issued: 1995-01-24

Synchronous semiconductor memory device

(Original Assignee) Mitsubishi Electric Corp     (Current Assignee) Mitsubishi Electric Corp

Yasuhiro Konishi, Takayuki Miyamoto, Takeshi Kajimoto, Hisashi Iwamoto
US6618736B1
CLAIM 1 . A method for file system creation (d line) and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5384745A
CLAIM 13 . The synchronous semiconductor memory device according to claim 1 , wherein each of said bank includes : a plurality of memory cells arranged in rows and columns , a plurality of word line (file system creation) s arranged corresponding to the rows for connecting memory cells on a corresponding row , a plurality of pairs of bit lines arranged corresponding to the columns for connecting memory cells on a corresponding column , a data line for transmitting data to and from a selected memory cell , column decode means responsive to an address signal for generating column selecting signal for selecting a column among the columns , connecting means responsive to the column selecting signal for connecting only one bit line of a pair of bit lines corresponding to the column selected by said column selecting signal .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (determined order) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5384745A
CLAIM 5 . The synchronous semiconductor memory device according to claim 4 , wherein each of said plurality of write register means includes a plurality of registers for storing the input data successively in a predetermined order (file systems, program code) .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (reading operation, write operation) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5384745A
CLAIM 1 . A synchronous semiconductor memory device taking in control signals and external signals including address signals having bank addresses and input data in synchronization with a clock signal in a form of a series of pulses , comprising : a memory cell array including a plurality of memory cells , said memory cell array including a plurality of banks activated for memory cell selection independent from each other in accordance with the bank addresses included in the address signals , and one of the bank addresses designating one of the banks ;
a plurality of write data register means provided corresponding to each of said plurality of banks for storing write data to the corresponding bank ;
and a plurality of read register means provided corresponding to each of said plurality of banks for storing data read from the corresponding bank , wherein a data read or write operation (storage unit writing module) is performed only for the one of the banks designated by the one of the bank addresses .

US5384745A
CLAIM 10 . The synchronous semiconductor memory device according to claim 1 , selection means responsive to an address for selecting a memory cell in said memory cell array ;
delay means for delaying a timing of activating the selection means in a data writing operation mode with respect to the timing of activation in a data reading operation (storage unit writing module) mode .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module (reading operation, write operation) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5384745A
CLAIM 1 . A synchronous semiconductor memory device taking in control signals and external signals including address signals having bank addresses and input data in synchronization with a clock signal in a form of a series of pulses , comprising : a memory cell array including a plurality of memory cells , said memory cell array including a plurality of banks activated for memory cell selection independent from each other in accordance with the bank addresses included in the address signals , and one of the bank addresses designating one of the banks ;
a plurality of write data register means provided corresponding to each of said plurality of banks for storing write data to the corresponding bank ;
and a plurality of read register means provided corresponding to each of said plurality of banks for storing data read from the corresponding bank , wherein a data read or write operation (storage unit writing module) is performed only for the one of the banks designated by the one of the bank addresses .

US5384745A
CLAIM 10 . The synchronous semiconductor memory device according to claim 1 , selection means responsive to an address for selecting a memory cell in said memory cell array ;
delay means for delaying a timing of activating the selection means in a data writing operation mode with respect to the timing of activation in a data reading operation (storage unit writing module) mode .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code (determined order) for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5384745A
CLAIM 5 . The synchronous semiconductor memory device according to claim 4 , wherein each of said plurality of write register means includes a plurality of registers for storing the input data successively in a predetermined order (file systems, program code) .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5323358A

Filed: 1993-03-01     Issued: 1994-06-21

Clock-synchronous semiconductor memory device and method for accessing the device

(Original Assignee) Toshiba Corp     (Current Assignee) Toshiba Corp

Haruki Toda, Yuji Watanabe, Hitoshi Kuyama, Shozo Saito
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (data items) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (data items) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (data items) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage (external sources) map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (data items) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage (external sources) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage (external sources) map comprises : initializing the second usage map to indicate that none of the storage units of the third set contain valid data . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (data items) from a storage unit of the first set ;

and in response to the second usage (external sources) map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (data items) from a storage unit of the first set ;

and in response to the second usage (external sources) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (data items) from a storage unit of the first set ;

and in response to the second usage (external sources) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage (external sources) map . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (data items) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (data items) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (data items) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage (external sources) map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (data items) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage (external sources) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set contains valid data . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage (external sources) map comprises : initializing the second usage map to indicate that none of the private storage units of the second set contain valid data . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (data items) from a shared storage unit ;

and in response to the second usage (external sources) map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (data items) from a shared storage unit ;

and in response to the second usage (external sources) map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (data items) from a shared storage unit ;

and in response to the second usage (external sources) map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage (external sources) map . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (data items) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (data items) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (data items) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage (external sources) map for indicating which storage units of third set contain valid data . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (data items) to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage (external sources) map that the corresponding storage unit of the third set contains valid data . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage (external sources) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage (external sources) map is initially reset to indicate that none of the storage units of the third set contain valid data . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (data items) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (external sources) map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (data items) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (external sources) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (data items) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (external sources) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (positive integer) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage (external sources) map . 		US5323358A
CLAIM 4 . A method for accessing a clock-synchronous semiconductor memory device comprising a plurality of memory cells arranged in matrix , the memory cells are divided into at least two blocks , access to the memory cells in these blocks is designated from address data input from external sources (second usage) , and access to the memory cell is executed synchronously with an externally-supplied clock signal , comprising the steps of : setting the other blocks in a precharged state or in a precharging standby indicating from outside of the semiconductor memory device while one block is being accessed ;
and setting the certain block in the access state immediately when the certain block is designated from the address data and if the certain block has been in the precharged state , wherein the designation of the block to be accessed is set using address data designating a block input from outside of the semiconductor memory device .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integer (storage unit update module) s) being set equal to the number of data items transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .

US6618736B1
CLAIM 53 . An computer program product (accessed data) for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (data items) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5323358A
CLAIM 5 . A clock-synchronous semiconductor memory device comprising : memory means comprising a plurality of memory cells arranged in a matrix , said memory cells being divided into a plurality of blocks ;
a plurality of registers used for data accessing between the memory means and an external device , which temporarily stores one part of the accessed data (computer program product) ;
scrambling means for selecting a part of the register used for storage of the accessed data and storing the part of accessed data ;
scrambler control means for controlling the operation of the scrambling means by which the accessed data is stored cyclically in a prescribed order in the respective registers for each cycle of the clock signal ;
and an output means for carrying out interchanges of the accessed data between the registers and the external device , wherein the scrambler control means sets the scrambling means to operate in the prescribed order each time a starting address for the data accessing is provided .

US5323358A
CLAIM 6 . A clock-synchronous semiconductor memory device as claimed in claim 5 , wherein the registers comprise a plurality of registers for input and a plurality of registers for output , the output registers being divided into register blocks of " ;
m" ;
groups made up of " ;
a" ;
registers each , with n=a×m (where m and n are positive integers) being set equal to the number of data items (data item) transferred for data access from the register blocks , and the count of the data items is stored in the registers for each " ;
a" ;
cycles of the clock signal , and the scrambler control means changes the state of the scrambling means each time data is stored .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5381376A

Filed: 1992-11-19     Issued: 1995-01-10

Video RAM having block selection function during serial write transfer operation

(Original Assignee) Samsung Electronics Co Ltd     (Current Assignee) Samsung Electronics Co Ltd

Min-Tae Kim, Dong-Jae Lee, Seung-Mo Seo
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (different one) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (different one) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set contains valid data . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (different one) ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (different one) ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (different one) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the third set contains valid data . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (different one) ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (different one) ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (different one) ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (different one) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (different one) of private storage units for the server . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (different one) of private storage units and the first usage map of a first server . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (transferring data) . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (different one) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (different one) does not contain valid data , reading the data item from the shared storage unit . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (different one) for which an indication of valid data is stored in the first usage map . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (different one) of private storage units with the second set of private storage units . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (different one) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (different one) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (write operation) for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operation (storage unit writing module) s ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (different one) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set contains valid data . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (different one) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (different one) ;

wherein the storage unit writing module (write operation) is further configured to write the data item to the corresponding storage unit (transferring data) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operation (storage unit writing module) s ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the third set contains valid data . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (different one) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5381376A
CLAIM 7 . A memory device for performing serial read and serial write data transfer operations , said memory device comprising : a random access memory comprising a plurality of blocks , each of said blocks of said random access memory having a plurality of memory cells in a matrix ;
a serial access memory comprising a plurality of blocks , each of said blocks of said serial access memory having a plurality of memory cells connected to each column of a different one (first set) of said blocks of said random access memory ;
block selection means for enabling said serial access memory to receive serial read data from said random access memory during serial read operations in response to address signals , and for enabling at least two of said blocks of said random access memory to receive serial write data from said serial access memory after said serial write data is written on all of said plurality of blocks of said serial access memory via a serial port during serial write operations ;
and data transfer means for transferring data (remote storage device, corresponding storage unit) between said random access memory and said serial access memory in response to said address signals .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5404463A

Filed: 1992-10-21     Issued: 1995-04-04

Method and apparatus for transferring data in portable image processing system

(Original Assignee) Eastman Kodak Co     (Current Assignee) Eastman Kodak Co

James E. McGarvey
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (other memory) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (other memory) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (other memory) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (other memory) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage (other memory) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (other memory) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (other memory) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage (other memory) map . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (other memory) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage (other memory) map of a first server . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (other memory) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (other memory) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (other memory) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (other memory) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (other memory) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (other memory) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set for which an indication of valid data is stored in the first usage (other memory) map . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (other memory) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module (other memory) for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (other memory) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (other memory) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (second diode) configured , in response to the first usage (other memory) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5404463A
CLAIM 3 . An improvement as in claim 2 , wherein the transfer control signal means comprises a transfer control signal line ;
wherein the first " ;
ready" ;
signal means comprises the memory having a first " ;
ready" ;
signal terminal ;
the second " ;
ready" ;
signal means comprises the other device having a second " ;
ready" ;
signal terminal ;
and wherein the AND-gate connection comprises the memory having a first " ;
enable" ;
signal terminal connected to the transfer control signal line , the other device having a second " ;
enable" ;
signal terminal connected to the transfer control signal line , a first diode connected between the first " ;
ready" ;
signal terminal and the first " ;
enable" ;
signal terminal , and a second diode (storage unit reading module, storage unit update module) connected between the second " ;
ready" ;
signal terminal and the second " ;
enable" ;
signal terminal .

US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (second diode) configured , in response to the first usage (other memory) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5404463A
CLAIM 3 . An improvement as in claim 2 , wherein the transfer control signal means comprises a transfer control signal line ;
wherein the first " ;
ready" ;
signal means comprises the memory having a first " ;
ready" ;
signal terminal ;
the second " ;
ready" ;
signal means comprises the other device having a second " ;
ready" ;
signal terminal ;
and wherein the AND-gate connection comprises the memory having a first " ;
enable" ;
signal terminal connected to the transfer control signal line , the other device having a second " ;
enable" ;
signal terminal connected to the transfer control signal line , a first diode connected between the first " ;
ready" ;
signal terminal and the first " ;
enable" ;
signal terminal , and a second diode (storage unit reading module, storage unit update module) connected between the second " ;
ready" ;
signal terminal and the second " ;
enable" ;
signal terminal .

US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module (other memory) is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (second diode) configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5404463A
CLAIM 3 . An improvement as in claim 2 , wherein the transfer control signal means comprises a transfer control signal line ;
wherein the first " ;
ready" ;
signal means comprises the memory having a first " ;
ready" ;
signal terminal ;
the second " ;
ready" ;
signal means comprises the other device having a second " ;
ready" ;
signal terminal ;
and wherein the AND-gate connection comprises the memory having a first " ;
enable" ;
signal terminal connected to the transfer control signal line , the other device having a second " ;
enable" ;
signal terminal connected to the transfer control signal line , a first diode connected between the first " ;
ready" ;
signal terminal and the first " ;
enable" ;
signal terminal , and a second diode (storage unit reading module, storage unit update module) connected between the second " ;
ready" ;
signal terminal and the second " ;
enable" ;
signal terminal .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (second diode) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (other memory) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5404463A
CLAIM 3 . An improvement as in claim 2 , wherein the transfer control signal means comprises a transfer control signal line ;
wherein the first " ;
ready" ;
signal means comprises the memory having a first " ;
ready" ;
signal terminal ;
the second " ;
ready" ;
signal means comprises the other device having a second " ;
ready" ;
signal terminal ;
and wherein the AND-gate connection comprises the memory having a first " ;
enable" ;
signal terminal connected to the transfer control signal line , the other device having a second " ;
enable" ;
signal terminal connected to the transfer control signal line , a first diode connected between the first " ;
ready" ;
signal terminal and the first " ;
enable" ;
signal terminal , and a second diode (storage unit reading module, storage unit update module) connected between the second " ;
ready" ;
signal terminal and the second " ;
enable" ;
signal terminal .

US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module (second diode) configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (other memory) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5404463A
CLAIM 3 . An improvement as in claim 2 , wherein the transfer control signal means comprises a transfer control signal line ;
wherein the first " ;
ready" ;
signal means comprises the memory having a first " ;
ready" ;
signal terminal ;
the second " ;
ready" ;
signal means comprises the other device having a second " ;
ready" ;
signal terminal ;
and wherein the AND-gate connection comprises the memory having a first " ;
enable" ;
signal terminal connected to the transfer control signal line , the other device having a second " ;
enable" ;
signal terminal connected to the transfer control signal line , a first diode connected between the first " ;
ready" ;
signal terminal and the first " ;
enable" ;
signal terminal , and a second diode (storage unit reading module, storage unit update module) connected between the second " ;
ready" ;
signal terminal and the second " ;
enable" ;
signal terminal .

US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage (other memory) map . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (second diode) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5404463A
CLAIM 3 . An improvement as in claim 2 , wherein the transfer control signal means comprises a transfer control signal line ;
wherein the first " ;
ready" ;
signal means comprises the memory having a first " ;
ready" ;
signal terminal ;
the second " ;
ready" ;
signal means comprises the other device having a second " ;
ready" ;
signal terminal ;
and wherein the AND-gate connection comprises the memory having a first " ;
enable" ;
signal terminal connected to the transfer control signal line , the other device having a second " ;
enable" ;
signal terminal connected to the transfer control signal line , a first diode connected between the first " ;
ready" ;
signal terminal and the first " ;
enable" ;
signal terminal , and a second diode (storage unit reading module, storage unit update module) connected between the second " ;
ready" ;
signal terminal and the second " ;
enable" ;
signal terminal .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (other memory) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5404463A
CLAIM 5 . An improvement as in claim 1 , wherein the other device is another memory (first usage, first usage map, usage map updating module) ;
the other device at least one storage location is another plurality of individually addressable data unit storage locations ;
and the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations , and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines ;
and means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5319755A

Filed: 1992-09-30     Issued: 1994-06-07

Integrated circuit I/O using high performance bus interface

(Original Assignee) Rambus Inc     (Current Assignee) Rambus Inc

Michael Farmwald, Mark Horowitz
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit (approximately two, plane orthogonal) of the first set corresponding to a storage unit of the second set ;

providing a first usage (time t) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (approximately two, plane orthogonal) of the second set contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (approximately two, plane orthogonal) of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (approximately two, plane orthogonal) of the first set ;

and in response to the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (approximately two, plane orthogonal) of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (approximately two, plane orthogonal) of the third set contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (approximately two, plane orthogonal) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (approximately two, plane orthogonal) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (approximately two, plane orthogonal) of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (approximately two, plane orthogonal) of the second set for which an indication of valid data is stored in the first usage (time t) map . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (approximately two, plane orthogonal) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit (approximately two, plane orthogonal) ;

and providing a first usage (time t) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage (time t) map of a first server . 		US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system for a second server (second access) using the stored template . 		US5319755A
CLAIM 51 . The apparatus of claim 33 for storing and retrieving data , wherein the first memory includes a first memory type register and a first access time register ;
the second memory includes a second memory type register and a second access (second server) time register .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (approximately two, plane orthogonal) contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (time t) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (approximately two, plane orthogonal) ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (approximately two, plane orthogonal) ;

and in response to the first usage (time t) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (approximately two, plane orthogonal) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (approximately two, plane orthogonal) of the second set contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (approximately two, plane orthogonal) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (approximately two, plane orthogonal) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (approximately two, plane orthogonal) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (time t) map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (approximately two, plane orthogonal) of the first set for which an indication of valid data is stored in the first usage (time t) map . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (approximately two, plane orthogonal) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (approximately two, plane orthogonal) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module (lower voltage) for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 32 . The apparatus of claim 22 for storing and retrieving data , wherein the first memory is a dynamic random access memory further comprising : (A) a plurality of sense amplifiers ;
(B) means to hold the sense amplifiers in an unmodified state after a selective read and write operation (storage unit writing module) , wherein the first memory is left in page mode ;
(C) means to precharge the sense amplifiers ;
(D) means for selecting whether to (1) precharge the sense amplifiers or (2) hold the sense amplifiers in an unmodified state .

US5319755A
CLAIM 56 . The apparatus of claim 5 for storing and retrieving data , wherein the low-voltage swing signals swing between an upper voltage and a lower voltage (usage map updating module) .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (time t) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (approximately two, plane orthogonal) of the second set contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (time t) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (approximately two, plane orthogonal) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (approximately two, plane orthogonal) of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (approximately two, plane orthogonal) of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (approximately two, plane orthogonal) of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module (lower voltage) is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 32 . The apparatus of claim 22 for storing and retrieving data , wherein the first memory is a dynamic random access memory further comprising : (A) a plurality of sense amplifiers ;
(B) means to hold the sense amplifiers in an unmodified state after a selective read and write operation (storage unit writing module) , wherein the first memory is left in page mode ;
(C) means to precharge the sense amplifiers ;
(D) means for selecting whether to (1) precharge the sense amplifiers or (2) hold the sense amplifiers in an unmodified state .

US5319755A
CLAIM 56 . The apparatus of claim 5 for storing and retrieving data , wherein the low-voltage swing signals swing between an upper voltage and a lower voltage (usage map updating module) .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (approximately two, plane orthogonal) of the third set contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (approximately two, plane orthogonal) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (approximately two, plane orthogonal) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (approximately two, plane orthogonal) of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (approximately two, plane orthogonal) of the second set for which an indication of valid data is stored in the first usage (time t) map . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (approximately two, plane orthogonal) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit (approximately two, plane orthogonal) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (time t) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5319755A
CLAIM 15 . The apparatus of claim 1 for storing and retrieving data , wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal (storage unit) to the first plane .

US5319755A
CLAIM 26 . The apparatus of claim 25 for storing and retrieving data , wherein the first memory further comprises : (A) a sense amplifier ;
(B) means for transferring a data block during the bus transaction ;
(C) response means , wherein the op code instructs the first memory to activate the response means , wherein the response means comprises means to (1) initiate the data block transfer ;
(2) select a size of the data block ;
(3) select a time t (first usage) o initiate the data block transfer ;
(4) access a control register ;
(5) precharge the sense amplifier before and after the data block transfer is complete ;
(6) hold data the sense amplifier after the data block transfer is complete ;
and (7) select normal and page-mode access .

US5319755A
CLAIM 57 . The apparatus of claim 56 for storing and retrieving data , wherein the upper voltage is approximately two (storage unit) volts .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5403639A

Filed: 1992-09-02     Issued: 1995-04-04

File server having snapshot application data groups

(Original Assignee) Oracle StorageTek     (Current Assignee) Oracle StorageTek

Jay S. Belsan, Jeffrey S. Laughlin, Mogens H. Pedersen, Robert J. Raicer, George A. Rudeseal, Charles P. Schafer, Barbara L. Steele, Patrick J. Tomsula
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (first set) of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets (identified set) of storage units are stored in a same storage device . 		US5403639A
CLAIM 7 . The file server system of claim 6 further comprising : means , responsive to a generation of a next duplicative data set pointer for an identified set (second sets) of data sets , for inserting said next duplicative data set pointer into a one of said series of data set pointers corresponding to said series associated with said identified set of data sets .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (first set) of storage units is stored in a local storage device and the second set (second set) of storage units is stored in a remote storage device . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (second set) contains valid data . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (second set) contain valid data . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (first set) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (first set) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first set) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set of physical data storage characteristics .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set of physical data storage characteristics .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (storage device) from a storage unit of the first set (first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (second set) of storage units with the third set of storage units . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (second set) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (first set) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set of physical data storage characteristics .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (first set) of private storage units for the server . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set of physical data storage characteristics .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (first set) of private storage units and the first usage map of a first server . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set of physical data storage characteristics .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (second set) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (storage device) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (second set) contains valid data . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (second set) contain valid data . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first set) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (storage device) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first set) does not contain valid data , reading the data item from the shared storage unit . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (first set) for which an indication of valid data is stored in the first usage map . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set of physical data storage characteristics .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (first set) of private storage units with the second set (second set) of private storage units . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (first set) that contain valid data to those corresponding private storage units of the second set (second set) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (first set) of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets (identified set) of storage units are stored in a same storage device . 		US5403639A
CLAIM 7 . The file server system of claim 6 further comprising : means , responsive to a generation of a next duplicative data set pointer for an identified set (second sets) of data sets , for inserting said next duplicative data set pointer into a one of said series of data set pointers corresponding to said series associated with said identified set of data sets .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (first set) of storage units is stored in a local storage device and the second set (second set) of storage units is stored in a remote storage device . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (second set) contains valid data . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (second set) contain valid data . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first set) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set of physical data storage characteristics .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (storage device) to a storage unit of the first set (first set) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set of physical data storage characteristics .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set of physical data storage characteristics .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (storage device) from a storage unit of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (second set) of storage units with the third set of storage units . 		US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (second set) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (positive integer) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5403639A
CLAIM 18 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage devices into m virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon , wherein m is a positive integer (storage unit update module) greater than one ;
and means for presenting a data storage image of n data storage volumes directly addressable by said at least one data processor , to said at least one data processor , wherein n is a positive integer greater than zero and less than m .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (first set) of storage units and a second set (second set) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (storage device) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5403639A
CLAIM 15 . The file server system of claim 1 wherein said maintaining means comprises : means for configuring said plurality of data storage device (data item) s into a plurality of virtual data storage volumes , each of said virtual data storage volumes being capable of storing at least one data set thereon ;
and means for presenting a data storage image of a selected one of said plurality of virtual data storage volumes to each of said at least one data processor .

US5403639A
CLAIM 20 . The file server system of claim 19 wherein said maintaining means further comprises : means for transferring said set of data sets containing said requested data set from a first data storage volume having a first set (first set) of physical data storage characteristics to a second data storage volume having a second set (second set) of physical data storage characteristics .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5365489A

Filed: 1992-05-01     Issued: 1994-11-15

Dual port video random access memory with block write capability

(Original Assignee) Samsung Electronics Co Ltd     (Current Assignee) Samsung Electronics Co Ltd

Seong-ouk Jeong
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map (memory block) for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map (memory block) comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map (memory block) indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map (memory block) indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map (memory block) for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map (memory block) comprises : initializing the second usage map to indicate that none of the storage units of the third set contain valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map (memory block) indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map (memory block) indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage map (memory block) . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map (memory block) . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map (memory block) for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage map (memory block) of a first server . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage map (memory block) comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage map (memory block) indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage map (memory block) indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map (memory block) for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map (memory block) comprises : initializing the second usage map to indicate that none of the private storage units of the second set contain valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map (memory block) indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map (memory block) indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map (memory block) indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map (memory block) indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map (memory block) indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set for which an indication of valid data is stored in the first usage map (memory block) . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map (memory block) . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map (memory block) for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module (memory block) for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map (memory block) is initially reset to indicate that none of the storage units of the second set contain valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map (memory block) indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map (memory block) indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage map (memory block) for indicating which storage units of third set contain valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module (memory block) is further configured to store an indication in the second usage map (memory block) that the corresponding storage unit of the third set contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map (memory block) is initially reset to indicate that none of the storage units of the third set contain valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map (memory block) indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map (memory block) indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage map (memory block) . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map (memory block) . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map (memory block) for indicating which storage units of the second set contain valid data ;

program code (write signal) for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5365489A
CLAIM 1 . A semiconductor memory device for performing a memory block (first usage map, second usage map, usage map updating module) write function , said semiconductor memory device comprising : a plurality of cell array blocks , each cell array block including a plurality of bit lines ;
a plurality of column select transistors coupled to said plurality of cell array blocks for selectively accessing corresponding ones of said plurality of bit lines ;
first decoding means , responsive to a first portion of a column address , for generating a first select signal for selecting one of said plurality of cell array blocks ;
second decoding means , responsive to a second portion of said column address , for generating a second select signal ;
multiplexing means for selectively outputting one of said second select signal and an external block write signal (program code) in response to a block write mode control signal ;
and a plurality of transfer transistors coupled to said multiplexing means and directly to said first decoding means , for driving select ones of said plurality of column select transistors in said selected one of said plurality of cell array blocks in response to said selectively multiplexed output of said multiplexing means .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5164916A

Filed: 1992-03-31     Issued: 1992-11-17

High-density double-sided multi-string memory module with resistor for insertion detection

(Original Assignee) Digital Equipment Corp     (Current Assignee) Samsung Electronics Co Ltd

Andrew L. Wu, Derrick D. DaCosta, Stephen R. Coe, Donald C. Pierce, II E. William Bruce
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (first set) of storage units and a second set (second set) of storage units , each storage unit (two rows) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (two rows) of the second set (second set) contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (two rows) of the first set (first set) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (two rows) of the first set (first set) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (two rows) of the third set corresponding to one of the storage units of the first set (first set) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (two rows) of the third set contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (two rows) of the first set (first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (two rows) of the first set (first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (two rows) of the first set (first set) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , reading the data item from the storage unit of the first set . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (two rows) of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (second set) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (two rows) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (first set) of private storage units , each of the private storage units corresponding to a shared storage unit (two rows) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (two rows) contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (two rows) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (two rows) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (second set) of private storage units , each private storage unit (two rows) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (two rows) of the second set (second set) contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (two rows) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (two rows) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first set) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (two rows) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (second set) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first set) does not contain valid data , reading the data item from the shared storage unit . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (two rows) of the first set (first set) for which an indication of valid data is stored in the first usage map . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (first set) that contain valid data to those corresponding private storage units of the second set (second set) that do not contain valid data ;

and for each private storage unit (two rows) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (first set) of storage units and a second set (second set) of storage units , each storage unit (two rows) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (two rows) of the second set (second set) contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (two rows) of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (two rows) of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (two rows) of the third set corresponding to one of the storage units of the first set (first set) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (two rows) of the first set (first set) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (two rows) of the third set contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (two rows) of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (two rows) of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (two rows) of the first set (first set) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (second set) does not contain valid data , to read the data item from the storage unit of the first set . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (two rows) of the second set (second set) for which an indication of valid data is stored in the first usage map . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (second set) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (two rows) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (first set) of storage units and a second set (second set) of storage units , each storage unit (two rows) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5164916A
CLAIM 9 . The memory module as claimed in claim 1 , wherein said first matrix includes two rows (storage unit) and eight columns of said chips , said second matrix includes two rows and eight columns of said chips , said first group includes eight of said chips , said second group includes eight of said chips , said third group includes eight of said chips , and said fourth group includes eight of said chips .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5276858A

Filed: 1991-12-26     Issued: 1994-01-04

Memory controller with integrated delay line circuitry

(Original Assignee) Intel Corp     (Current Assignee) Intel Corp

Jayawant V. Oak, Robert N. Murdoch, Craig S. Walker, Thomas Heil, Erez Carmel
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item (microprocessor function) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (microprocessor function) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item (microprocessor function) from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item (microprocessor function) to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (microprocessor function) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (microprocessor function) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item (microprocessor function) from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item (microprocessor function) to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set of private storage units and the first usage map of a first server (second request) . 		US5276858A
CLAIM 7 . The memory controller apparatus of claim 1 , wherein the memory controller apparatus includes a first port coupled to the microprocessor , a second port coupled to the plurality of peripheral devices , wherein the first port receives a first request from the microprocessor and the second port receives a second request (first server) from one of the plurality of peripheral devices .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (microprocessor function) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item (microprocessor function) from a shared storage unit ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item (microprocessor function) to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (microprocessor function) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (microprocessor function) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item (microprocessor function) from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item (microprocessor function) to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module (timing parameters) for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US5276858A
CLAIM 13 . The memory controller apparatus of claim 12 , further comprising programmable timing register means for storing timing parameters (usage map updating module) of the memory timing control signals , wherein the multiplexing means of the delay line means is coupled to the programmable timing register means , wherein the multiplexing means of the delay line means is controlled by the timing parameters to select the memory timing control signals , wherein the timing parameters can be changed by reprogramming by software .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (microprocessor function) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item (microprocessor function) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item (microprocessor function) to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module (timing parameters) is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US5276858A
CLAIM 13 . The memory controller apparatus of claim 12 , further comprising programmable timing register means for storing timing parameters (usage map updating module) of the memory timing control signals , wherein the multiplexing means of the delay line means is coupled to the programmable timing register means , wherein the multiplexing means of the delay line means is controlled by the timing parameters to select the memory timing control signals , wherein the timing parameters can be changed by reprogramming by software .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (microprocessor function) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (microprocessor function) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item (microprocessor function) from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item (microprocessor function) to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5276858A
CLAIM 1 . A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of peripheral devices , wherein the memory controller apparatus interfaces the microprocessor and the plurality of peripheral devices , wherein the microprocessor function (data item) s asynchronously with the plurality of peripheral devices , the memory controller apparatus comprising : (A) delay line means coupled to receive a selected request from one of the microprocessor and the plurality of peripheral devices for generating a plurality of memory timing control signals when the selected request is for access to the memory array , wherein the memory timing control signals are used for accessing the memory array , wherein the delay line means functions independently of any clock signal , wherein the delay line means is only triggered by the selected request ;
and (B) memory state circuitry coupled to the delay line means for controlling sequence and timing of the memory timing control signals , wherein the memory state circuitry is clocked by the memory timing control signals .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5345573A

Filed: 1991-10-04     Issued: 1994-09-06

High speed burst read address generation with high speed transfer

(Original Assignee) Bull HN Information Systems Inc     (Current Assignee) Bull HN Information Systems Inc

Raymond D. Bowden, III, Chester M. Nibby, Jr.
US6618736B1
CLAIM 1 . A method for file system (data sections) creation (data sections) and archival comprising : providing a first set (different one, first number) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5345573A
CLAIM 1 . A system comprising : a synchronous bus having address , command and data sections (file system creation, file systems, file system) and operating according to a predetermined bus protocol ;
a unit coupled to said bus for generating commands for reading and writing memory , one of said commands specifying a burst operation in which any one of a plurality of predetermined sequences of addresses having a different initial address is supplied to said bus by said unit during a plurality of successive memory read cycles of operation ;
and a memory tightly coupled to said unit through said synchronous bus , said memory comprising : a pair of dynamic random access memories (DRAMs) coupled to said bus , said DRAMs being organized for storing data words having even and odd addresses for enabling read out of a plurality of words during each memory read cycle of operation , each of said DRAMs having an identical width , the sum of the widths being no more than twice as wide as said data section of said bus and each DRAM including first and second data output circuits for receiving said plurality of data words read out during a predetermined number of successive memory read cycles of operation , said first and second data output circuits including a plurality of transparent latch circuits and tristate buffer driver circuits respectively ;
an address register for storing said initial address of each of said plurality of predetermined address sequences ;
and , address sequence control circuit means coupled to said DRAMs , said address sequence control circuit means including : first logic circuit means coupled to said address register , said first logic circuit means for selectively generating an output control signal for modifying the state of a first predetermined address bit signal of an initial address supplied to said DRAMs during a predetermined one of said number of said successive cycles of operation for generating all of said addresses for a first number (first set) of said plurality of predetermined address sequences ;
and , second logic circuit means coupled to said address section of said bus and to said plurality of said transparent latch circuits and said tristate buffer driver circuits of said first and second output data circuits respectively , of each of said DRAMs , said second logic circuit means including means for storing an indication of the state of a second predetermined address bit signal of said initial address of said one of said predetermined address sequences and means for selectively enabling different one (first set) s of said first and second data output circuits of said each of said DRAMs as a function of said state of said indication of said state of said second address bit signal stored by said means for storing during said predetermined number of said successive cycles of operation for transferring data (remote storage device, corresponding storage unit) read out to said output data circuits during a plurality of bus cycles in an order corresponding to said addresses of a second number of said plurality of address sequences and which enables immediate transfer of pairs of said data words through said tristate buffer driver circuits .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (different one, first number) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		US5345573A
CLAIM 1 . A system comprising : a synchronous bus having address , command and data sections and operating according to a predetermined bus protocol ;
a unit coupled to said bus for generating commands for reading and writing memory , one of said commands specifying a burst operation in which any one of a plurality of predetermined sequences of addresses having a different initial address is supplied to said bus by said unit during a plurality of successive memory read cycles of operation ;
and a memory tightly coupled to said unit through said synchronous bus , said memory comprising : a pair of dynamic random access memories (DRAMs) coupled to said bus , said DRAMs being organized for storing data words having even and odd addresses for enabling read out of a plurality of words during each memory read cycle of operation , each of said DRAMs having an identical width , the sum of the widths being no more than twice as wide as said data section of said bus and each DRAM including first and second data output circuits for receiving said plurality of data words read out during a predetermined number of successive memory read cycles of operation , said first and second data output circuits including a plurality of transparent latch circuits and tristate buffer driver circuits respectively ;
an address register for storing said initial address of each of said plurality of predetermined address sequences ;
and , address sequence control circuit means coupled to said DRAMs , said address sequence control circuit means including : first logic circuit means coupled to said address register , said first logic circuit means for selectively generating an output control signal for modifying the state of a first predetermined address bit signal of an initial address supplied to said DRAMs during a predetermined one of said number of said successive cycles of operation for generating all of said addresses for a first number (first set) of said plurality of predetermined address sequences ;
and , second logic circuit means coupled to said address section of said bus and to said plurality of said transparent latch circuits and said tristate buffer driver circuits of said first and second output data circuits respectively , of each of said DRAMs , said second logic circuit means including means for storing an indication of the state of a second predetermined address bit signal of said initial address of said one of said predetermined address sequences and means for selectively enabling different one (first set) s of said first and second data output circuits of said each of said DRAMs as a function of said state of said indication of said state of said second address bit signal stored by said means for storing during said predetermined number of said successive cycles of operation for transferring data (remote storage device, corresponding storage unit) read out to said output data circuits during a plurality of bus cycles in an order corresponding to said addresses of a second number of said plurality of address sequences and which enables immediate transfer of pairs of said data words through said tristate buffer driver circuits .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units (latch circuits) of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5345573A
CLAIM 2 . The system of claim 1 wherein said DRAMs are enabled so that a first pair of said plurality of words read out during a first memory cycle of operation are stored in said plurality of transparent latch circuits (corresponding storage units) and a next pair of said plurality of words read out during a next memory cycle of operation are supplied to said plurality of tristate buffer driver circuits for immediate transfer under control of said second logic circuit means .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units (latch circuits) of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5345573A
CLAIM 2 . The system of claim 1 wherein said DRAMs are enabled so that a first pair of said plurality of words read out during a first memory cycle of operation are stored in said plurality of transparent latch circuits (corresponding storage units) and a next pair of said plurality of words read out during a next memory cycle of operation are supplied to said plurality of tristate buffer driver circuits for immediate transfer under control of said second logic circuit means .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system (data sections) within at least one storage device comprising a first set (different one, first number) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code (data word) for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5345573A
CLAIM 4 . The system of claim 3 wherein said system further includes increment/decrement circuit means connected to said address register , to said DRAMs , and to said address sequence control circuit means , said increment/decrement circuit means inverting said state of said first predetermined address bit signal in response to said output control signal for modifying said state of said first predetermined address bit during said second interval of said predetermined number of said successive memory read cycles of operation for addressing a different group of data word (program code) s .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5124589A

Filed: 1991-04-25     Issued: 1992-06-23

Semiconductor integrated circuit capable of synchronous and asynchronous operations and operating method therefor

(Original Assignee) Mitsubishi Electric Corp     (Current Assignee) Mitsubishi Electric Corp

Toru Shiomi, Shigeki Ohbayashi, Atsushi Ohba
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage (accessible memory) map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage (accessible memory) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage (accessible memory) map comprises : initializing the second usage map to indicate that none of the storage units of the third set contain valid data . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage (accessible memory) map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage (accessible memory) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage (accessible memory) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units (latch circuits) of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage (accessible memory) map . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US5124589A
CLAIM 22 . A semiconductor integrated circuit including a functional circuit (7 , 10) operable in synchronous and asynchronous modes , comprising : an internal clock signal generating means (9) for generating internal clock signals in response to externally applied clock signals ;
input and output latch circuits (corresponding storage units) (8' ;
, 11' ;
) responsive to said internal clock signal for enabling latching and throughputting of input and output signals applied to and provided by said functional circuit in a synchronous mode of operation ;
and asynchronous operation mode control means (950 , 92 ;
109 ;
109' ;
;
161 , 161' ;
) for selectively disabling latching by said input and output latch circuit of said input and output signals .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage (accessible memory) map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage (accessible memory) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set contains valid data . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage (accessible memory) map comprises : initializing the second usage map to indicate that none of the private storage units of the second set contain valid data . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (accessible memory) map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (accessible memory) map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (accessible memory) map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage (accessible memory) map . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage (accessible memory) map for indicating which storage units of third set contain valid data . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage (accessible memory) map that the corresponding storage unit of the third set contains valid data . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage (accessible memory) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage (accessible memory) map is initially reset to indicate that none of the storage units of the third set contain valid data . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (accessible memory) map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (accessible memory) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (accessible memory) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units (latch circuits) of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage (accessible memory) map . 		US5124589A
CLAIM 21 . A method for operating a semiconductor integrated circuit , said semiconductor integrated circuit including a randomly accessible memory (second usage) device (7) , an input circuit (8' ;
) responsive to an externally supplied input signal for generating an internal input signal and supplying the internal input signal to said memory device , and an output circuit (11' ;
) for producing output data from data output from said memory device , comprising the steps of : operating , in response to an externally supplied clock signal and a first level of an externally supplied control signal , said input circuit and said output circuit in synchronization with said clock signal ;
and operating , in response to a second level of the externally supplied control signal , both said input circuit and said output circuit to allow signals supplied thereto to pass therethrough .

US5124589A
CLAIM 22 . A semiconductor integrated circuit including a functional circuit (7 , 10) operable in synchronous and asynchronous modes , comprising : an internal clock signal generating means (9) for generating internal clock signals in response to externally applied clock signals ;
input and output latch circuits (corresponding storage units) (8' ;
, 11' ;
) responsive to said internal clock signal for enabling latching and throughputting of input and output signals applied to and provided by said functional circuit in a synchronous mode of operation ;
and asynchronous operation mode control means (950 , 92 ;
109 ;
109' ;
;
161 , 161' ;
) for selectively disabling latching by said input and output latch circuit of said input and output signals .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		WO9116680A1

Filed: 1991-04-16     Issued: 1991-10-31

Integrated circuit i/o using a high preformance bus interface

(Original Assignee) Rambus Inc.     

Michael Farmwald, Mark Horowitz
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (different one, more memory, first one) of storage units and a second set (different one, more memory, first one) of storage units , each storage unit (plane orthogonal) of the first set corresponding to a storage unit of the second set ;

providing a first usage (time t) map (memory block) for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets (more lines) of storage units are stored in a same storage device . 		WO9116680A1
CLAIM 114 . A semiconductor device capable of use in an architecture for a semiconductor system bus including a plurality of semiconductor devices connected in parallel to a bus wherein said bus system includes a plurality of bus lines for carrying substantially all address , data , control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said system bus , and has substantially fewer bus lines than the number of bits in a single address , and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device , said semiconductor device comprising connection means adapted to connect said semiconductor device to said system bus , an internal input/output bus within said semiconductor device having more lines (second sets) than said system bus , and a means for multiplexing the lines of said internal bus to the lines of said system bus , whereby said system bus can run at a higher speed than said internal bus .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (different one, more memory, first one) of storage units is stored in a local storage device and the second set (different one, more memory, first one) of storage units is stored in a remote storage device . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (time t) map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (plane orthogonal) of the second set (different one, more memory, first one) contains valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (time t) map (memory block) comprises : initializing the first usage map to indicate that none of the storage units of the second set (different one, more memory, first one) contain valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (plane orthogonal) of the first set (different one, more memory, first one) ;

and in response to the first usage (time t) map (memory block) indicating that the corresponding storage unit of the second set (different one, more memory, first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (plane orthogonal) of the first set (different one, more memory, first one) ;

and in response to the first usage (time t) map (memory block) indicating that the corresponding storage unit of the second set (different one, more memory, first one) does not contain valid data , reading the data item from the storage unit of the first set . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (plane orthogonal) of the third set corresponding to one of the storage units of the first set (different one, more memory, first one) ;

providing a second usage map (memory block) for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (plane orthogonal) of the third set contains valid data . 		WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map (memory block) comprises : initializing the second usage map to indicate that none of the storage units of the third set contain valid data . 		WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (plane orthogonal) of the first set (different one, more memory, first one) ;

and in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (plane orthogonal) of the first set (different one, more memory, first one) ;

and in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map (memory block) indicating that the corresponding storage unit of the second set (different one, more memory, first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (plane orthogonal) of the first set (different one, more memory, first one) ;

and in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map (memory block) indicating that the corresponding storage unit of the second set (different one, more memory, first one) does not contain valid data , reading the data item from the storage unit of the first set . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (plane orthogonal) of the second set (different one, more memory, first one) for which an indication of valid data is stored in the first usage (time t) map (memory block) . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (different one, more memory, first one) of storage units with the third set of storage units . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (different one, more memory, first one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (plane orthogonal) of the second set that is copied , storing an indication of valid data in the second usage map (memory block) . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems (I/O interface) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (different one, more memory, first one) of private storage units , each of the private storage units corresponding to a shared storage unit (plane orthogonal) ;

and providing a first usage (time t) map (memory block) for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 9 . The system of claim 8 wherein said peripheral device is selected from the group consisting of an I/O interface (archiving file systems) port , a video controller and a disk controller .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (different one, more memory, first one) of private storage units for the server . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (different one, more memory, first one) of private storage units and the first usage (time t) map (memory block) of a first server . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (time t) map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (plane orthogonal) contains valid data . 		WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (time t) map (memory block) comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (plane orthogonal) ;

and in response to the first usage (time t) map (memory block) indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (plane orthogonal) ;

and in response to the first usage (time t) map (memory block) indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (different one, more memory, first one) of private storage units , each private storage unit (plane orthogonal) of the second set corresponding to one of the shared storage units ;

providing a second usage map (memory block) for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (plane orthogonal) of the second set (different one, more memory, first one) contains valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map (memory block) comprises : initializing the second usage map to indicate that none of the private storage units of the second set (different one, more memory, first one) contain valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (plane orthogonal) ;

and in response to the second usage map (memory block) indicating that the corresponding private storage unit of the second set (different one, more memory, first one) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (plane orthogonal) ;

and in response to the second usage map (memory block) indicating that the corresponding private storage unit of the second set (different one, more memory, first one) does not contain valid data and the first usage (time t) map (memory block) indicating that the corresponding private storage unit of the first set (different one, more memory, first one) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (plane orthogonal) ;

and in response to the second usage map (memory block) indicating that the corresponding private storage unit of the second set (different one, more memory, first one) does not contain valid data and the first usage (time t) map (memory block) indicating that the corresponding private storage unit of the first set (different one, more memory, first one) does not contain valid data , reading the data item from the shared storage unit . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (plane orthogonal) of the first set (different one, more memory, first one) for which an indication of valid data is stored in the first usage (time t) map (memory block) . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (different one, more memory, first one) of private storage units with the second set (different one, more memory, first one) of private storage units . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (different one, more memory, first one) that contain valid data to those corresponding private storage units of the second set (different one, more memory, first one) that do not contain valid data ;

and for each private storage unit (plane orthogonal) of the first set that is copied , storing an indication of valid data in the second usage map (memory block) . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (different one, more memory, first one) of storage units and a second set (different one, more memory, first one) of storage units , each storage unit (plane orthogonal) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (time t) map (memory block) for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module (memory block) for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 37 . The bus subsystem of claim 36 wherein , for a data block transfer , said master device and said memory device use the same access time and same data block size regardless of whether said data block transfer is a read or write operation (storage unit writing module) .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 37 . The system of claim 36 , wherein the first and second sets (more lines) of storage units are stored in a same storage device . 		WO9116680A1
CLAIM 114 . A semiconductor device capable of use in an architecture for a semiconductor system bus including a plurality of semiconductor devices connected in parallel to a bus wherein said bus system includes a plurality of bus lines for carrying substantially all address , data , control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said system bus , and has substantially fewer bus lines than the number of bits in a single address , and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device , said semiconductor device comprising connection means adapted to connect said semiconductor device to said system bus , an internal input/output bus within said semiconductor device having more lines (second sets) than said system bus , and a means for multiplexing the lines of said internal bus to the lines of said system bus , whereby said system bus can run at a higher speed than said internal bus .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (different one, more memory, first one) of storage units is stored in a local storage device and the second set (different one, more memory, first one) of storage units is stored in a remote storage device . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (time t) map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (plane orthogonal) of the second set (different one, more memory, first one) contains valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (time t) map (memory block) is initially reset to indicate that none of the storage units of the second set (different one, more memory, first one) contain valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (plane orthogonal) of the first set (different one, more memory, first one) , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map (memory block) indicating that the corresponding storage unit of the second set (different one, more memory, first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (plane orthogonal) of the first set (different one, more memory, first one) , the system further comprising : a storage unit reading module configured , in response to the first usage (time t) map (memory block) indicating that the corresponding storage unit of the second set (different one, more memory, first one) does not contain valid data , to read the data item from the storage unit of the first set . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (plane orthogonal) of the third set corresponding to one of the storage units of the first set (different one, more memory, first one) , the system further comprising a second usage map (memory block) for indicating which storage units of third set contain valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (plane orthogonal) of the first set (different one, more memory, first one) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module (memory block) is further configured to store an indication in the second usage map (memory block) that the corresponding storage unit of the third set contains valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 37 . The bus subsystem of claim 36 wherein , for a data block transfer , said master device and said memory device use the same access time and same data block size regardless of whether said data block transfer is a read or write operation (storage unit writing module) .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map (memory block) comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (plane orthogonal) of the third set contains valid data . 		WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage map (memory block) is initially reset to indicate that none of the storage units of the third set contain valid data . 		WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (plane orthogonal) of the first set (different one, more memory, first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (plane orthogonal) of the first set (different one, more memory, first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map (memory block) indicating that the corresponding storage unit of the second set (different one, more memory, first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (plane orthogonal) of the first set (different one, more memory, first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map (memory block) indicating that the corresponding storage unit of the third set does not contain valid data and the first usage (time t) map (memory block) indicating that the corresponding storage unit of the second set (different one, more memory, first one) does not contain valid data , to read the data item from the storage unit of the first set . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (plane orthogonal) of the second set (different one, more memory, first one) for which an indication of valid data is stored in the first usage (time t) map (memory block) . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (different one, more memory, first one) of storage units with the third set of storage units . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (different one, more memory, first one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (plane orthogonal) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map (memory block) . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (different one, more memory, first one) of storage units and a second set (different one, more memory, first one) of storage units , each storage unit (plane orthogonal) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (time t) map (memory block) for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		WO9116680A1
CLAIM 4 . A system comprising a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device , a transceiver bus connecting said transceiver devices , and a means for transferring information between each of said buses of said memory subsystems and said transceiver bus , whereby memory subsystems may be integrated into a larger system having more memory (first set, second set) than an individual memory subsystem .

WO9116680A1
CLAIM 11 . The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal (storage unit) to said subsystem bus plane .

WO9116680A1
CLAIM 20 . The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section , whereby memory may be organized into one or a small number of contiguous memory block (first usage map, second usage map, usage map updating module) s .

WO9116680A1
CLAIM 31 . The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device , and wherein said op code instructs said memory device to activate a response means , said response means including a means to initiate a data block transfer , select the size of said data block , select the time t (first usage) o initiate said data block transfer , access a control register , including reading from or writing to said control register , precharge said sense amplifiers after each of said data block transfers is complete , hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete , or select normal or page-mode access .

WO9116680A1
CLAIM 52 . The bus subsystem of claim 47 wherein said arbitration means comprises a means included in a first one (first set, second set) of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets , a means for assigning a priority to each said master device which sent a colliding request packet , and a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority .

WO9116680A1
CLAIM 89 . The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one (first set, second set) of said rows .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5379438A

Filed: 1990-12-14     Issued: 1995-01-03

Transferring a processing unit's data between substrates in a parallel processor

(Original Assignee) Xerox Corp     (Current Assignee) Xerox Corp

Alan G. Bell, John Lamping
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (first one) of storage units and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (first one) of storage units is stored in a local storage device and the second set (first one) of storage units is stored in a remote storage device (transferring data) . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set (first one) contains valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units of the second set (first one) contain valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set (first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set (first one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first one) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (first one) for which an indication of valid data is stored in the first usage map . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (first one) of storage units with the third set of storage units . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set (first one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (first one) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (first one) of private storage units for the server . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (first one) of private storage units and the first usage map of a first server . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (first one) of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (first one) contains valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units of the second set (first one) contain valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (first one) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (first one) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first one) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (first one) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first one) does not contain valid data , reading the data item from the shared storage unit . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (first one) for which an indication of valid data is stored in the first usage map . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (first one) of private storage units with the second set (first one) of private storage units . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (first one) that contain valid data to those corresponding private storage units of the second set (first one) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (first one) of storage units and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (first one) of storage units is stored in a local storage device and the second set (first one) of storage units is stored in a remote storage device (transferring data) . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set (first one) contains valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units of the second set (first one) contain valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set (first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set (first one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (first one) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (first one) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (transferring data) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (first one) for which an indication of valid data is stored in the first usage map . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (first one) of storage units with the third set of storage units . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set (first one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module (transfer command) is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5379438A
CLAIM 5 . The method of claim 4 in which the substep of operating the respective external transfer circuitry to transmit the first subset count data and the second subset count data comprises substeps of : providing a first count transfer command (storage unit update module) to control the respective external transfer circuitry of the first substrate to transmit the first subset count data and to cause the respective external transfer circuitry of the second substrate to receive the first subset count data ;
and providing a second count transfer command to control the respective external transfer circuitry of the second substrate to transmit the second subset count data and to cause the respective external transfer circuitry of the first substrate to receive the second subset count data .

US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (first one) of storage units and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5379438A
CLAIM 11 . The method of claim 7 in which the respective data of a first one (first set, second set) of the processing units that is in the respective set of valid processing units of one of the substrates indicates a first combination of values in which a first one of the variables is not assigned a value ;
at least one of the substeps of performing an operation that modifies the respective set of valid processing units comprising substeps of : copying the respective data of the first processing unit to a second one of the processing units that is not in the respective set of valid processing units of the substrate so that the second processing unit is added to the respective set of valid processing units ;
and modifying the respective data of at least one of the first and second processing units after the copying step so that the first variable is assigned different values in the first and second processing units and so that the respective data of the first and second processing units indicate different subcombinations of the first combination of values .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5117389A

Filed: 1990-09-05     Issued: 1992-05-26

Flat-cell read-only-memory integrated circuit

(Original Assignee) Macronix International Co Ltd     (Current Assignee) Macronix International Co Ltd

Tom D. H. Yiu
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (first one) of storage units (storage units) and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US5117389A
CLAIM 10 . A memory circuit on a semiconductor substrate ;
comprising : a plurality of local bit lines LBL n , for n equal to 0 through N-1 , each comprising a buried diffusion region in the substrate ;
an insulating layer of essentially constant thickness over the local bit lines ;
a plurality of word lines WL m , for m equal to 1 through M , on the insulating layer , the plurality of word lines intersecting the local bit lines , so that regions between respective pairs of local bit lines and under word lines , form channels of field effect transistors , whereby a column of flat cell ROM storage units (storage units) is formed between each pair of local bit lines ;
a plurality of global bit lines isolated from the plurality of word lines , the global bit lines comprising essentially straight conductive strips for a length extending across the plurality of word lines WL m , for m equal to 1 through M , a first subset of the global bit lines forming data lines and a second subset of the global bit lines forming virtual ground lines ;
a block select line ;
a first plurality of block select transistor , each having a drain connected to one of the global bit lines forming data lines , a source connected to a respective one of the local bit lines LBL 4k+1 , for k equal to 0 through (N-1)/4 , and a gate connected to the block select line ;
a second plurality of block select transistors , each having a drain connected to one of the global bit lines forming virtual ground lines , a source connected to a respective one of local bit lines LBL 4k+3 , for k equal to 0 through (N-1)/4 , and a gate connected to the block select line ;
and a bank left select word line and a bank right select word line , on the insulating layer , intersecting the plurality of local bit lines and defining bank left and bank right select transistors between each pair of local bit lines and under the bank left select and bank right select word lines ;
wherein the bank left and bank right select transistors are fixed coded to couple local bit lines LBL 2j , for j equal to 0 through (N-1)/2 , to a data line through another local bit line LBL 2j ±1 in response to energizing voltage on the bank left select word line , or to couple local bit lines LBL 2j , for j equal to 0 through (N-1)/2 , to a virtual ground line through another local bit line LBL 2j ±1 in response to energizing voltage on the bank right select word line .

US6618736B1
CLAIM 2 . The method of claim 1 , wherein the first and second sets of storage units (storage units) are stored in a same storage device . 		US5117389A
CLAIM 10 . A memory circuit on a semiconductor substrate ;
comprising : a plurality of local bit lines LBL n , for n equal to 0 through N-1 , each comprising a buried diffusion region in the substrate ;
an insulating layer of essentially constant thickness over the local bit lines ;
a plurality of word lines WL m , for m equal to 1 through M , on the insulating layer , the plurality of word lines intersecting the local bit lines , so that regions between respective pairs of local bit lines and under word lines , form channels of field effect transistors , whereby a column of flat cell ROM storage units (storage units) is formed between each pair of local bit lines ;
a plurality of global bit lines isolated from the plurality of word lines , the global bit lines comprising essentially straight conductive strips for a length extending across the plurality of word lines WL m , for m equal to 1 through M , a first subset of the global bit lines forming data lines and a second subset of the global bit lines forming virtual ground lines ;
a block select line ;
a first plurality of block select transistor , each having a drain connected to one of the global bit lines forming data lines , a source connected to a respective one of the local bit lines LBL 4k+1 , for k equal to 0 through (N-1)/4 , and a gate connected to the block select line ;
a second plurality of block select transistors , each having a drain connected to one of the global bit lines forming virtual ground lines , a source connected to a respective one of local bit lines LBL 4k+3 , for k equal to 0 through (N-1)/4 , and a gate connected to the block select line ;
and a bank left select word line and a bank right select word line , on the insulating layer , intersecting the plurality of local bit lines and defining bank left and bank right select transistors between each pair of local bit lines and under the bank left select and bank right select word lines ;
wherein the bank left and bank right select transistors are fixed coded to couple local bit lines LBL 2j , for j equal to 0 through (N-1)/2 , to a data line through another local bit line LBL 2j ±1 in response to energizing voltage on the bank left select word line , or to couple local bit lines LBL 2j , for j equal to 0 through (N-1)/2 , to a virtual ground line through another local bit line LBL 2j ±1 in response to energizing voltage on the bank right select word line .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (first one) of storage units (storage units) is stored in a local storage device and the second set (first one) of storage units is stored in a remote storage device . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US5117389A
CLAIM 10 . A memory circuit on a semiconductor substrate ;
comprising : a plurality of local bit lines LBL n , for n equal to 0 through N-1 , each comprising a buried diffusion region in the substrate ;
an insulating layer of essentially constant thickness over the local bit lines ;
a plurality of word lines WL m , for m equal to 1 through M , on the insulating layer , the plurality of word lines intersecting the local bit lines , so that regions between respective pairs of local bit lines and under word lines , form channels of field effect transistors , whereby a column of flat cell ROM storage units (storage units) is formed between each pair of local bit lines ;
a plurality of global bit lines isolated from the plurality of word lines , the global bit lines comprising essentially straight conductive strips for a length extending across the plurality of word lines WL m , for m equal to 1 through M , a first subset of the global bit lines forming data lines and a second subset of the global bit lines forming virtual ground lines ;
a block select line ;
a first plurality of block select transistor , each having a drain connected to one of the global bit lines forming data lines , a source connected to a respective one of the local bit lines LBL 4k+1 , for k equal to 0 through (N-1)/4 , and a gate connected to the block select line ;
a second plurality of block select transistors , each having a drain connected to one of the global bit lines forming virtual ground lines , a source connected to a respective one of local bit lines LBL 4k+3 , for k equal to 0 through (N-1)/4 , and a gate connected to the block select line ;
and a bank left select word line and a bank right select word line , on the insulating layer , intersecting the plurality of local bit lines and defining bank left and bank right select transistors between each pair of local bit lines and under the bank left select and bank right select word lines ;
wherein the bank left and bank right select transistors are fixed coded to couple local bit lines LBL 2j , for j equal to 0 through (N-1)/2 , to a data line through another local bit line LBL 2j ±1 in response to energizing voltage on the bank left select word line , or to couple local bit lines LBL 2j , for j equal to 0 through (N-1)/2 , to a virtual ground line through another local bit line LBL 2j ±1 in response to energizing voltage on the bank right select word line .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (first one) contains valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage map comprises : initializing the first usage map to indicate that none of the storage units (storage units) of the second set (first one) contain valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US5117389A
CLAIM 10 . A memory circuit on a semiconductor substrate ;
comprising : a plurality of local bit lines LBL n , for n equal to 0 through N-1 , each comprising a buried diffusion region in the substrate ;
an insulating layer of essentially constant thickness over the local bit lines ;
a plurality of word lines WL m , for m equal to 1 through M , on the insulating layer , the plurality of word lines intersecting the local bit lines , so that regions between respective pairs of local bit lines and under word lines , form channels of field effect transistors , whereby a column of flat cell ROM storage units (storage units) is formed between each pair of local bit lines ;
a plurality of global bit lines isolated from the plurality of word lines , the global bit lines comprising essentially straight conductive strips for a length extending across the plurality of word lines WL m , for m equal to 1 through M , a first subset of the global bit lines forming data lines and a second subset of the global bit lines forming virtual ground lines ;
a block select line ;
a first plurality of block select transistor , each having a drain connected to one of the global bit lines forming data lines , a source connected to a respective one of the local bit lines LBL 4k+1 , for k equal to 0 through (N-1)/4 , and a gate connected to the block select line ;
a second plurality of block select transistors , each having a drain connected to one of the global bit lines forming virtual ground lines , a source connected to a respective one of local bit lines LBL 4k+3 , for k equal to 0 through (N-1)/4 , and a gate connected to the block select line ;
and a bank left select word line and a bank right select word line , on the insulating layer , intersecting the plurality of local bit lines and defining bank left and bank right select transistors between each pair of local bit lines and under the bank left select and bank right select word lines ;
wherein the bank left and bank right select transistors are fixed coded to couple local bit lines LBL 2j , for j equal to 0 through (N-1)/2 , to a data line through another local bit line LBL 2j ±1 in response to energizing voltage on the bank left select word line , or to couple local bit lines LBL 2j , for j equal to 0 through (N-1)/2 , to a virtual ground line through another local bit line LBL 2j ±1 in response to energizing voltage on the bank right select word line .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units (storage units) , each storage unit of the third set corresponding to one of the storage units of the first set (first one) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US5117389A
CLAIM 10 . A memory circuit on a semiconductor substrate ;
comprising : a plurality of local bit lines LBL n , for n equal to 0 through N-1 , each comprising a buried diffusion region in the substrate ;
an insulating layer of essentially constant thickness over the local bit lines ;
a plurality of word lines WL m , for m equal to 1 through M , on the insulating layer , the plurality of word lines intersecting the local bit lines , so that regions between respective pairs of local bit lines and under word lines , form channels of field effect transistors , whereby a column of flat cell ROM storage units (storage units) is formed between each pair of local bit lines ;
a plurality of global bit lines isolated from the plurality of word lines , the global bit lines comprising essentially straight conductive strips for a length extending across the plurality of word lines WL m , for m equal to 1 through M , a first subset of the global bit lines forming data lines and a second subset of the global bit lines forming virtual ground lines ;
a block select line ;
a first plurality of block select transistor , each having a drain connected to one of the global bit lines forming data lines , a source connected to a respective one of the local bit lines LBL 4k+1 , for k equal to 0 through (N-1)/4 , and a gate connected to the block select line ;
a second plurality of block select transistors , each having a drain connected to one of the global bit lines forming virtual ground lines , a source connected to a respective one of local bit lines LBL 4k+3 , for k equal to 0 through (N-1)/4 , and a gate connected to the block select line ;
and a bank left select word line and a bank right select word line , on the insulating layer , intersecting the plurality of local bit lines and defining bank left and bank right select transistors between each pair of local bit lines and under the bank left select and bank right select word lines ;
wherein the bank left and bank right select transistors are fixed coded to couple local bit lines LBL 2j , for j equal to 0 through (N-1)/2 , to a data line through another local bit line LBL 2j ±1 in response to energizing voltage on the bank left select word line , or to couple local bit lines LBL 2j , for j equal to 0 through (N-1)/2 , to a virtual ground line through another local bit line LBL 2j ±1 in response to energizing voltage on the bank right select word line .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the storage units (storage units) of the third set contain valid data . 		US5117389A
CLAIM 10 . A memory circuit on a semiconductor substrate ;
comprising : a plurality of local bit lines LBL n , for n equal to 0 through N-1 , each comprising a buried diffusion region in the substrate ;
an insulating layer of essentially constant thickness over the local bit lines ;
a plurality of word lines WL m , for m equal to 1 through M , on the insulating layer , the plurality of word lines intersecting the local bit lines , so that regions between respective pairs of local bit lines and under word lines , form channels of field effect transistors , whereby a column of flat cell ROM storage units (storage units) is formed between each pair of local bit lines ;
a plurality of global bit lines isolated from the plurality of word lines , the global bit lines comprising essentially straight conductive strips for a length extending across the plurality of word lines WL m , for m equal to 1 through M , a first subset of the global bit lines forming data lines and a second subset of the global bit lines forming virtual ground lines ;
a block select line ;
a first plurality of block select transistor , each having a drain connected to one of the global bit lines forming data lines , a source connected to a respective one of the local bit lines LBL 4k+1 , for k equal to 0 through (N-1)/4 , and a gate connected to the block select line ;
a second plurality of block select transistors , each having a drain connected to one of the global bit lines forming virtual ground lines , a source connected to a respective one of local bit lines LBL 4k+3 , for k equal to 0 through (N-1)/4 , and a gate connected to the block select line ;
and a bank left select word line and a bank right select word line , on the insulating layer , intersecting the plurality of local bit lines and defining bank left and bank right select transistors between each pair of local bit lines and under the bank left select and bank right select word lines ;
wherein the bank left and bank right select transistors are fixed coded to couple local bit lines LBL 2j , for j equal to 0 through (N-1)/2 , to a data line through another local bit line LBL 2j ±1 in response to energizing voltage on the bank left select word line , or to couple local bit lines LBL 2j , for j equal to 0 through (N-1)/2 , to a virtual ground line through another local bit line LBL 2j ±1 in response to energizing voltage on the bank right select word line .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (first one) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , reading the data item from the storage unit of the first set . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set (first one) for which an indication of valid data is stored in the first usage map . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 15 . The method of claim 14 , further comprising : merging the second set (first one) of storage units (storage units) with the third set of storage units . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units (storage units) of the second set (first one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage map . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units (storage units) ;

for each of the plurality of servers : providing a first set (first one) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units (storage units) and the first set (first one) of private storage units for the server . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (first one) of private storage units (storage units) and the first usage map of a first server . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set (first one) of private storage units (storage units) , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set (first one) contains valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage map comprises : initializing the second usage map to indicate that none of the private storage units (storage units) of the second set (first one) contain valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (first one) contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (first one) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first one) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set (first one) does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (first one) does not contain valid data , reading the data item from the shared storage unit . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (first one) for which an indication of valid data is stored in the first usage map . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (first one) of private storage units (storage units) with the second set (first one) of private storage units . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units (storage units) of the first set (first one) that contain valid data to those corresponding private storage units of the second set (first one) that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (first one) of storage units (storage units) and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module (first subset) for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (first one) of storage units (storage units) is stored in a local storage device and the second set (first one) of storage units is stored in a remote storage device . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the second set (first one) contains valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage map is initially reset to indicate that none of the storage units (storage units) of the second set (first one) contain valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units (storage units) , each storage unit of the third set corresponding to one of the storage units of the first set (first one) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (first one) ;

wherein the storage unit writing module (first subset) is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (first one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set (first one) does not contain valid data , to read the data item from the storage unit of the first set . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set (first one) for which an indication of valid data is stored in the first usage map . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 51 . The system of claim 50 , further comprising : a merging module configured to merge the second set (first one) of storage units (storage units) with the third set of storage units . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units (storage units) of the second set (first one) that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (first one) of storage units (storage units) and a second set (first one) of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5117389A
CLAIM 7 . The memory circuit of claim 6 , wherein the means for selectively coupling includes : code implants in the channels along a first one (first set, second set) of the first plurality of conductive strips defining alternately conductive then non-conductive states to couple a first buried diffusion region to a center buried diffusion region , and isolate the center buried diffusion region from a third buried diffusion region , and couple the third buried diffusion region to a next center buried diffusion region , and so on within the section , code implants in the channels along a second one of the first plurality of conductive strips defining alternately non-conductive then conductive states to isolate the first buried diffusion region from the center buried diffusion region , and couple the center buried diffusion region to the third buried diffusion region , and isolate the third buried diffusion region from a next center buried diffusion region , and so on within the section , and wherein code implants in the channels along others of the first plurality of conductive strips define stored data ;
and the source of each of the plurality of block select transistors is coupled to one of the center buried diffusion regions .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5077693A

Filed: 1990-08-06     Issued: 1991-12-31

Dynamic random access memory

(Original Assignee) Motorola Solutions Inc     (Current Assignee) Apple Inc ; NXP USA Inc

Kim C. Hardee, David B. Chapman, Juan Pineda
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (selected word line) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (selected word line) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (selected word line) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (selected word line) ;

and in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (selected word line) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (selected word line) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (selected word line) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (selected word line) ;

and in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (selected word line) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (selected word line) of private storage units for the server . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (selected word line) of private storage units and the first usage map of a first server . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (selected word line) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (selected word line) does not contain valid data , reading the data item from the shared storage unit . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (selected word line) for which an indication of valid data is stored in the first usage map . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (selected word line) of private storage units with the second set of private storage units . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (selected word line) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (selected word line) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (selected word line) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (selected word line) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (selected word line) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (selected word line) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (selected word line) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (selected word line) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (selected word line) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (selected word line) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (selected word line) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code (write signal) for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5077693A
CLAIM 1 . A dynamic random access memory comprising : a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells located at respective intersections of said bit lines and said word lines , each of said memory cells providing a signal to its respective bit line indicative of data stored therein in response to its respective word line being enabled ;
address input means for sequentially receiving a row address and a column address , providing said row address as an output in response to an edge of an external clock signal while a row enable signal is in a first state and a column enable signal is in a second state , and providing said column address as an output in response to said column enable signal being in said first state on a sequential edge of said external clock signal ;
row decoder means for enabling a selected word line (first set) in response to receiving said row address from said address input means ;
a plurality of sense amplifiers , coupled to respective bit lines , each of said sense amplifiers provided to amplify said signal on said respective bit line provided by said memory cell coupled to said respective bit line and said enabled word line ;
column decoder means for coupling a selected bit line to a common data line in response to receiving said column address signal from said address input means and for decoupling said selected bit line from said common data line when said row enable and said column enable signals are both in said second state on an edge of said external clock signal ;
a secondary sense amplifier coupled to said common data line for amplifying said signal coupled to said common data line from said selected bit line and for providing an output indicative thereof ;
and output means for coupling said output of said secondary sense amplifier to an output of said memory in response to an edge of said external clock signal .

US5077693A
CLAIM 6 . In a memory having a plurality of bit lines ;
a plurality of word lines intersecting said plurality of bit lines ;
a plurality of refreshable memory cells coupled to respective bit and word lines at intersections thereof , each memory cell providing a signal indicative of data stored therein to said bit line to which it is coupled in response to said word line to which it is coupled being enabled ;
a plurality of sense amplifiers coupled to respective bit lines , each of said sense amplifiers for amplifying said signal provided by said memory cell coupled to said respective bit line ;
and a secondary amplifier coupled to a data line for amplifying a signal coupled thereto , a method for reading a data from said memory cells comprising the steps of : a) providing a write signal (program code) of a second state so that said data will be read from said memory cells ;
b) providing a column enable signal of a second state and a row enable signal of a first state ;
c) latching a row address into a row address buffer on an edge of an external clock signal while said row enable signal is in said first state and said column enable signal is in said second state ;
d) providing said column enable signal of a first state following the latching of said row address ;
e) latching a column address into a column address buffer on an edge of said external clock signal while said row and column enable signals are in said first state ;
and f) reading said data from said memory cells corresponding to said row address and said column address .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5179687A

Filed: 1990-06-25     Issued: 1993-01-12

Semiconductor memory device containing a cache and an operation method thereof

(Original Assignee) Mitsubishi Electric Corp     (Current Assignee) Mitsubishi Electric Corp

Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura
US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage (accessible memory) map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage (accessible memory) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 10 . The method of claim 8 , wherein providing a second usage (accessible memory) map comprises : initializing the second usage map to indicate that none of the storage units of the third set contain valid data . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage (accessible memory) map indicating that the corresponding storage unit of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage (accessible memory) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage (accessible memory) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit of the second set that is copied , storing an indication of valid data in the second usage (accessible memory) map . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage (accessible memory) map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage (accessible memory) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit of the second set contains valid data . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 29 . The method of claim 27 , wherein providing a second usage (accessible memory) map comprises : initializing the second usage map to indicate that none of the private storage units of the second set contain valid data . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (accessible memory) map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (accessible memory) map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage (accessible memory) map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set does not contain valid data , reading the data item from the shared storage unit . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage (accessible memory) map . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set , the system further comprising a second usage (accessible memory) map for indicating which storage units of third set contain valid data . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage (accessible memory) map that the corresponding storage unit of the third set contains valid data . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage (accessible memory) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit of the third set contains valid data . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 46 . The system of claim 44 , wherein the second usage (accessible memory) map is initially reset to indicate that none of the storage units of the third set contain valid data . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (accessible memory) map indicating that the corresponding storage unit of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (accessible memory) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage (accessible memory) map indicating that the corresponding storage unit of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage (accessible memory) map . 		US5179687A
CLAIM 10 . A method for operating a cache memory system including at least one randomly accessible memory (second usage) device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns and divided into a plurality of memory cell blocks , a plurality of sense amplifiers corresponding to the columns of said memory cell array for detecting and amplifying and latching data on said columns and a plurality of data latch means corresponding to the columns in said memory cell array and provided separately from said sense amplifiers each for receiving data on a corresponding column to latch the received data , said cache memory system further including means for generating a cache hit/miss indicating signal indicating whether at least one of data stored in said data latches is requested to be accessed , said method including the steps of : applying to said memory device a row address strobe signal for providing a row address strobe timing in response to said cache hit/miss indicating signal ;
isolating said plurality of data latch means from said plurality of sense amplifiers in response to said row address strobe signal indicative of a cache hit ;
selecting one of said memory cell blocks in response to said row address strobe signal indicating a cache miss to transfer the data latched by said sense amplifiers included in the selected block , thereby to replace the contents of the data latches with the transferred data , based on a block select address included in an externally applied column address ;
accessing data stored in at least one of the data latch means provided for said selected block in response to said externally applied column address when said row address strobe signal indicating the cache hit is received ;
and accessing data latched by at least one of said sense amplifiers in response to said column address when said row address strobe signal indicating the cache miss is received .

US6618736B1
CLAIM 53 . An computer program product (data latches) for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5179687A
CLAIM 5 . A semiconductor memory device in accordance with claim 1 , wherein each said storage means comprises data latches (computer program product) provided in one-to-one correspondence for the columns in said memory cell array , and said first and second means are in common provided with column selector means for selecting at least one column corresponding to an externally applied column address .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5111386A

Filed: 1990-06-14     Issued: 1992-05-05

Cache contained type semiconductor memory device and operating method therefor

(Original Assignee) Mitsubishi Electric Corp     (Current Assignee) Mitsubishi Electric Corp

Kazuyasu Fujishima, Charles A. Hart
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (selected word line) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage (transfer gate transistors) map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (selected word line) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage (transfer gate transistors) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set contains valid data . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 5 . The method of claim 1 , wherein providing a first usage (transfer gate transistors) map comprises : initializing the first usage map to indicate that none of the storage units of the second set contain valid data . 		US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (selected word line) ;

and in response to the first usage (transfer gate transistors) map indicating that the corresponding storage unit (transferring data) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (selected word line) ;

and in response to the first usage (transfer gate transistors) map indicating that the corresponding storage unit (transferring data) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (selected word line) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the third set contains valid data . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (selected word line) ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (selected word line) ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage (transfer gate transistors) map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set (selected word line) ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage (transfer gate transistors) map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit of the second set for which an indication of valid data is stored in the first usage (transfer gate transistors) map . 		US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (selected word line) of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage (transfer gate transistors) map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (selected word line) of private storage units for the server . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (selected word line) of private storage units and the first usage (transfer gate transistors) map of a first server . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (transferring data) . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage (transfer gate transistors) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit contains valid data . 		US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 24 . The method of claim 17 , wherein providing a first usage (transfer gate transistors) map comprises : initializing the first usage map to indicate that none of the private storage units contain valid data . 		US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (transfer gate transistors) map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the first usage (transfer gate transistors) map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (transfer gate transistors) map indicating that the corresponding private storage unit of the first set (selected word line) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage (transfer gate transistors) map indicating that the corresponding private storage unit of the first set (selected word line) does not contain valid data , reading the data item from the shared storage unit . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit of the first set (selected word line) for which an indication of valid data is stored in the first usage (transfer gate transistors) map . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (selected word line) of private storage units with the second set of private storage units . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (selected word line) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit of the first set that is copied , storing an indication of valid data in the second usage map . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (selected word line) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage (transfer gate transistors) map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (selected word line) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage (transfer gate transistors) map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set contains valid data . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 40 . The system of claim 36 , wherein the first usage (transfer gate transistors) map is initially reset to indicate that none of the storage units of the second set contain valid data . 		US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (selected word line) , the system further comprising : a storage unit reading module configured , in response to the first usage (transfer gate transistors) map indicating that the corresponding storage unit (transferring data) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (selected word line) , the system further comprising : a storage unit reading module configured , in response to the first usage (transfer gate transistors) map indicating that the corresponding storage unit (transferring data) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set (selected word line) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set (selected word line) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (transferring data) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the third set contains valid data . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (selected word line) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (selected word line) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage (transfer gate transistors) map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5111386A
CLAIM 1 . A semiconductor memory device for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , word lines corresponding to said rows , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
sense amplifier means for amplifying and latching data of a row of memory cells corresponding to a selected word line (first set) ;
cache storage means , separate from said sense amplifier means , and provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal and externally applied row and column address , said second means including transfer means for transferring data (remote storage device, corresponding storage unit) from a block of said memory cell array to said cache storage means ;
and third means responsive to said cache miss indicating signal , said third means including means for controlling the data transfer operation of said transfer means in response to a part of said externally applied column address , wherein only a part of data on said row corresponding to the selected word line in said memory cell array is transferred through said transfer means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set (selected word line) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage (transfer gate transistors) map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5111386A
CLAIM 4 . A semiconductor memory device containing a cache memory therein for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
cache storage means provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal ;
and means responsive to said cache miss indicating signal for transferring data (remote storage device, corresponding storage unit) from one of said memory cell blocks to the corresponding cache storage means to replace the data therein , and wherein said second means comprises : means for selecting a cell block in response to a block select signal included in an externally applied column address , said means being activated in response to said cache miss signal ;
means for connecting the selected cell block to the corresponding block of said data storage means in response to the block select signal from said block selecting means ;
and means responsive to the externally applied column address for selectively reading out data from the corresponding position in the selected block of said data storage means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit of the second set for which an indication of valid data is stored in the first usage (transfer gate transistors) map . 		US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .

US6618736B1
CLAIM 53 . An computer program product (data latches) for creating and archiving a file system within at least one storage device comprising a first set (selected word line) of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage (transfer gate transistors) map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5111386A
CLAIM 3 . A semiconductor memory device in accordance with claim 1 , wherein said cache storage means comprises a plurality of data latches (computer program product) each provided for each column in said memory cell array .

US5111386A
CLAIM 4 . A semiconductor memory device containing a cache memory therein for use in a cache system including a generator for generating a cache hit/miss indicating signal , comprising : a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns , said memory cell array divided into a plurality of memory cell blocks each corresponding to a grouping of columns ;
cache storage means provided for each said memory cell block for storing data of the corresponding cell block ;
said generator generating a cache hit indicating signal when an externally applied address matches an address related to information in the cache storage means and generating a cache miss indicating signal when no such match occurs ;
first means for accessing data , corresponding to an externally applied column address , from said cache storage means in response to said cache hit indicating signal ;
second means for directly accessing data from said memory cell array in response to said cache miss indicating signal ;
and means responsive to said cache miss indicating signal for transferring data (remote storage device, corresponding storage unit) from one of said memory cell blocks to the corresponding cache storage means to replace the data therein , and wherein said second means comprises : means for selecting a cell block in response to a block select signal included in an externally applied column address , said means being activated in response to said cache miss signal ;
means for connecting the selected cell block to the corresponding block of said data storage means in response to the block select signal from said block selecting means ;
and means responsive to the externally applied column address for selectively reading out data from the corresponding position in the selected block of said data storage means .

US5111386A
CLAIM 5 . A semiconductor memory device in accordance with claim 4 , wherein said means for connecting comprises a plurality of transfer gate transistors (first usage, first usage map) each provided for each column in the memory cell array to be turned on and off in response to said block select signal .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5276867A

Filed: 1989-12-19     Issued: 1994-01-04

Digital data storage system with improved data migration

(Original Assignee) Epoch Systems Inc     (Current Assignee) Epoch Systems Inc

Gregory Kenley, George Ericson, Richard Fortier, Chuck Holland, Robert Mastors, James Pownell, Tracy Taylor, John Wallace, Neil Webber
US6618736B1
CLAIM 17 . A method for creating and archiving file systems (file systems) of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set of private storage units , each of the private storage units corresponding to a shared storage unit ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5276867A
CLAIM 5 . Apparatus according to claim 2 , including means for grouping said files into a plurality of file systems (file systems) , the total number of said file systems being less than the number of said files , and said file selection means including means responsive to selected file attributes for selecting particular files of said file systems to be migrated .

US6618736B1
CLAIM 20 . The method of claim 19 , further comprising : creating a file system for a second server (client devices, second access) using the stored template . 		US5276867A
CLAIM 32 . Apparatus according to claim 1 , wherein said file migration means includes prestage reserve means for migrating , periodically , selected files from said secondary storage means to said backing store means without releasing storage locations on said secondary storage means associated with said selected files , so that client devices (second server) can continue to operate upon said selected files , and so that storage locations in said secondary storage means , occupied by unmodified ones of said selected files may be released immediately in response to a storage utilization level exceeding a selected high-water-mark level .

US5276867A
CLAIM 35 . A method for improving backup performance and for providing access to migrated digital files , the method comprising the steps of configuring a primary storage element to have a first quantity of storage locations and a first access speed , to store a first plurality of digital files , configuring a secondary storage means to have a second quantity of storage locations , greater than the first quantity of storage locations , and a second access (second server) speed , slower than the first access speed , to store a second plurality of digital files , configuring a backing store element to have a third quantity of storage locations , greater than the second quantity of storage locations , and a third access speed , slower than the second access speed , to store a third plurality of digital files , configuring each of the digital files , included in the first , second , and third plurality of digital files , to have an associated characteristic , including , file attributes including at least one of , file name , file size , file owner , file protections , time elapsed since a previous access , and type of access , detecting how many of the second plurality of storage locations are being used for storing digital files , generating a secondary-storage-full signal when more than a preset number of the second plurality of storage locations are being so used , automatically migrating digital files from the secondary storage means to the backing store element at selected times , the migration step including the steps of selecting , in response to the secondary-storage-full signal , digital files to be migrated from the secondary storage means to the backing store element , staging-out digital files , selected by the selecting step , from the secondary storage element to the backing store means , retrieving from said primary storage means , digital files having a first associated characteristic storing copies thereof , and generating signals representative of storage locations of respect ones of said copies , wherein said copies are referred to as baseline-backup copies , retrieving from said primary storage means , digital files for which baseline-backup copies are not stored , or for which baseline-backup copies are not stored , but which have been updated since a time of their retrieval from said primary storage means for storage as baseline-backup copies , and storing , along with the full-backup copies , the file identifiers and the storage locating-representative signals associated with files for which baseline-backup copies are stored , but which have not been updated since a time of their retrieval from said primary storage means by said baseline-backup means for storing as baseline-backup copies , wherein said storage location-representative signals are indicative of where the baseline-backup copies are stored .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US4937734A

Filed: 1989-06-28     Issued: 1990-06-26

High speed bus with virtual memory data transfer and rerun cycle capability

(Original Assignee) Sun Microsystems Inc     (Current Assignee) Sun Microsystems Inc

Andreas Bechtolsheim
US6618736B1
CLAIM 1 . A method for file system creation (d line) and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US4937734A
CLAIM 4 . The method of claim 3 , wherein said bus further includes a clock signal line coupled to each of said agents and to a bus clock , and wherein all signals on said line (file system creation) s of said bus change synchronously with a rising edge of a clock signal provided by said bus clock on said clock signal line .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set contains valid data . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the third set contains valid data . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (transferring data) . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the second set contains valid data . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (transferring data) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (transferring data) of the third set contains valid data . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US4937734A
CLAIM 1 . In a computer bus having agents selectively coupled to a bus , an improved method of transferring data (remote storage device, corresponding storage unit) among such agents comprising the steps of : transmitting a virtual address from an accessing agent to a memory management unit (MMU) coupled to said bus , said memory management unit including storage means for storing translation data for translating said virtual address into a real address ;
transmitting a rerun signal from said MMU to said accessing agent if said MMU does not have translation data for said virtual address stored in said storage means ;
granting control of said bus to said MMU ;
transferring the translation data for said virtual address from an external peripheral device to said MMU ;
retransmitting said virtual address to said MMU from said accessing agent ;
translating said virtual address into a physical address ;
transferring said data between said accessing agent to a memory location corresponding to said physical address .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5097489A

Filed: 1989-05-19     Issued: 1992-03-17

Method for incorporating window strobe in a data synchronizer

(Original Assignee) National Semiconductor Corp     (Current Assignee) National Semiconductor Corp

Patrick A. Tucci
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (controlling means) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means) of the second set contains valid data . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (controlling means) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the first usage map indicating that the corresponding storage unit (controlling means) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit of the third set corresponding to one of the storage units of the first set ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (controlling means) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means) of the third set contains valid data . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit of the first set ;

and in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (controlling means) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (controlling means) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means) of the second set contains valid data . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (controlling means) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (controlling means) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit of the first set ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (controlling means) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (controlling means) of the third set contains valid data . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit of the first set , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (controlling means) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .

US6618736B1
CLAIM 53 . An computer program product (first input) for creating and archiving a file system within at least one storage device comprising a first set of storage units and a second set of storage units , each storage unit of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (controlling means) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5097489A
CLAIM 1 . A data synchronizer for synchronizing input data to a VCO signal , comprising : a VCO with a control input and a VCO output for providing said VCO signal ;
means for receiving said input data on an input line ;
a phase comparator with a first input (computer program product) and second input and phase difference output , with said first input coupled to receive a signal from said receiving means , at a delay of substantially one-half of a VCO signal period ;
said second input coupled through a pulse gate to said VCO output , said pulse gate coupled for activation by said input data on said input line ;
and said phase difference output coupled through a filter means to said control input of said VCO ;
a flip-flop , with a data input coupled to receive a signal from said receiving means , and a clock input coupled to clock said data input on opposite phase to said VCO signal ;
and means for controlling the relative timing between the signal to said first input of said phase comparator and the signal to said data input of said flip-flop .

US5097489A
CLAIM 2 . The data synchronizer as in claim 1 wherein said controlling means (corresponding storage unit) comprises a tapped delay line , wherein said first input of said phase comparator is coupled to a first tap and said data input of said flip-flop is coupled to a second tap of said tapped delay line .




US6618736B1

Filed: 2001-03-09     Issued: 2003-09-09

Template-based creation and archival of file systems

(Original Assignee) Ensim Corp     (Current Assignee) Intellectual Ventures I LLC

Paul Menage		US5001672A

Filed: 1989-05-16     Issued: 1991-03-19

Video ram with external select of active serial access register

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Timothy J. Ebbers, Satish Gupta, Randall L. Henderson, Nathan R. Hiltebeitel, Robert Tamlyn, Steven W. Tomashot, Todd Williams
US6618736B1
CLAIM 1 . A method for file system creation and archival comprising : providing a first set (different one) of storage units and a second set of storage units , each storage unit (counter means) of the first set corresponding to a storage unit of the second set ;

providing a first usage map for indicating which storage units of the second set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 3 . The method of claim 1 , wherein the first set (different one) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 4 . The method of claim 1 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (counter means) (transferring data) of the second set contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 6 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (counter means) of the first set (different one) ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 7 . The method of claim 1 , further comprising : intercepting an attempt to read a data item from a storage unit (counter means) of the first set (different one) ;

and in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 8 . The method of claim 1 , further comprising : providing a third set of storage units , each storage unit (counter means) of the third set corresponding to one of the storage units of the first set (different one) ;

providing a second usage map for indicating which storage units of third set contain valid data ;

intercepting an attempt to write a data item to a storage unit of the first set ;

writing the data item to the corresponding storage unit (transferring data) of the third set ;

and storing an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 9 . The method of claim 8 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (counter means) (transferring data) of the third set contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 11 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (counter means) of the first set (different one) ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , reading the data item from the corresponding storage unit of the third set . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 12 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (counter means) of the first set (different one) ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , reading the data item from the corresponding storage unit of the second set . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 13 . The method of claim 8 , further comprising : intercepting an attempt to read a data item from a storage unit (counter means) of the first set (different one) ;

and in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , reading the data item from the storage unit of the first set . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 14 . The method of claim 8 , further comprising : archiving each storage unit (counter means) of the second set for which an indication of valid data is stored in the first usage map . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 16 . The method of claim 15 , wherein merging comprises : copying the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and for each storage unit (counter means) of the second set that is copied , storing an indication of valid data in the second usage map . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 17 . A method for creating and archiving file systems of a plurality of servers , the method comprising : providing a set of shared storage units ;

for each of the plurality of servers : providing a first set (different one) of private storage units , each of the private storage units corresponding to a shared storage unit (counter means) ;

and providing a first usage map for indicating which of the private storage units contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding private storage unit ;

and storing an indication in the first usage map that the corresponding private storage unit contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 18 . The method of claim 17 , wherein the file system of each server comprises a combination of the set of shared storage units and the first set (different one) of private storage units for the server . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 19 . The method of claim 17 , further comprising : storing a template comprising a copy of the first set (different one) of private storage units and the first usage map of a first server . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 22 . The method of claim 17 , wherein the shared storage units are stored a local storage device and the private storage units are stored in a remote storage device (transferring data) . 		US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 23 . The method of claim 17 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (counter means) contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 25 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (counter means) ;

and in response to the first usage map indicating that the corresponding private storage unit contains valid data , reading the data item from the corresponding private storage unit . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 26 . The method of claim 17 , further comprising : intercepting an attempt to read a data item from a shared storage unit (counter means) ;

and in response to the first usage map indicating that the corresponding private storage unit does not contain valid data , reading the data item from the shared storage unit . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 27 . The method of claim 17 , further comprising : providing a second set of private storage units , each private storage unit (counter means) of the second set corresponding to one of the shared storage units ;

providing a second usage map for indicating which private storage units of second set contain valid data ;

intercepting an attempt to write a data item to a shared storage unit ;

writing the data item to the corresponding storage unit (transferring data) of the second set ;

and storing an indication in the second usage map that the corresponding storage unit of the second set contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 28 . The method of claim 27 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding private storage unit (counter means) of the second set contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 30 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (counter means) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set contains valid data , reading the data item from the corresponding private storage unit of the second set . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 31 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (counter means) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (different one) contains valid data , reading the data item from the corresponding private storage unit of the first set . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 32 . The method of claim 27 , further comprising : intercepting an attempt to read a data item from a shared storage unit (counter means) ;

and in response to the second usage map indicating that the corresponding private storage unit of the second set does not contain valid data and the first usage map indicating that the corresponding private storage unit of the first set (different one) does not contain valid data , reading the data item from the shared storage unit . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 33 . The method of claim 27 , further comprising : archiving each private storage unit (counter means) of the first set (different one) for which an indication of valid data is stored in the first usage map . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 34 . The method of claim 33 , further comprising : merging the first set (different one) of private storage units with the second set of private storage units . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 35 . The method of claim 34 , wherein merging comprises : copying the private storage units of the first set (different one) that contain valid data to those corresponding private storage units of the second set that do not contain valid data ;

and for each private storage unit (counter means) of the first set that is copied , storing an indication of valid data in the second usage map . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 36 . A system for creating and archiving a file system within at least one storage device comprising a first set (different one) of storage units and a second set of storage units , each storage unit (counter means) of the first set corresponding to a storage unit of the second set , the system comprising : a first usage map for indicating which storage units of the second set contain valid data ;

an interception module for intercepting an attempt to write a data item to a storage unit of the first set ;

a storage unit writing module for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and a usage map updating module for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 38 . The system of claim 36 , wherein the first set (different one) of storage units is stored in a local storage device and the second set of storage units is stored in a remote storage device (transferring data) . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 39 . The system of claim 36 , wherein the first usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (counter means) (transferring data) of the second set contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 41 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (counter means) of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 42 . The system of claim 36 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (counter means) of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the first usage map indicating that the corresponding storage unit (transferring data) of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 43 . The system of claim 36 , wherein the at least one storage device further comprises a third set of storage units , each storage unit (counter means) of the third set corresponding to one of the storage units of the first set (different one) , the system further comprising a second usage map for indicating which storage units of third set contain valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 44 . The system of claim 43 , wherein the interception module is further configured to intercept an attempt to write a data item to a storage unit (counter means) of the first set (different one) ;

wherein the storage unit writing module is further configured to write the data item to the corresponding storage unit (transferring data) of the third set ;

and wherein the usage map updating module is further configured to store an indication in the second usage map that the corresponding storage unit of the third set contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

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CLAIM 45 . The system of claim 44 , wherein the second usage map comprises a bitmap , each bit of the bitmap indicating whether a corresponding storage unit (counter means) (transferring data) of the third set contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 47 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (counter means) of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set contains valid data , to read the data item from the corresponding storage unit of the third set . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

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CLAIM 48 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (counter means) of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set contains valid data , to read the data item from the corresponding storage unit of the second set . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

US6618736B1
CLAIM 49 . The system of claim 44 , wherein the interception module is further configured to intercept an attempt to read a data item from a storage unit (counter means) of the first set (different one) , the system further comprising : a storage unit reading module configured , in response to the second usage map indicating that the corresponding storage unit (transferring data) of the third set does not contain valid data and the first usage map indicating that the corresponding storage unit of the second set does not contain valid data , to read the data item from the storage unit of the first set . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .

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CLAIM 50 . The system of claim 44 , further comprising : an archival module configured to archive each storage unit (counter means) of the second set for which an indication of valid data is stored in the first usage map . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

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CLAIM 52 . The system of claim 51 , wherein the merging module is further configured to copy the storage units of the second set that contain valid data to those corresponding storage units of the third set that do not contain valid data ;

and wherein the storage unit (counter means) update module is configured , for each storage unit of the second set that is copied , to store an indication of valid data in the second usage map . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US6618736B1
CLAIM 53 . An computer program product for creating and archiving a file system within at least one storage device comprising a first set (different one) of storage units and a second set of storage units , each storage unit (counter means) of the first set corresponding to a storage unit of the second set , the computer program product comprising : a first usage map for indicating which storage units of the second set contain valid data ;

program code for intercepting an attempt to write a data item to a storage unit of the first set ;

program code for writing the data item to the corresponding storage unit (transferring data) of the second set ;

and program code for storing an indication in the first usage map that the corresponding storage unit of the second set contains valid data . 		US5001672A
CLAIM 1 . A dual-port memory comprising : a memory array having a plurality of memory elements each of which is accessed at random by a row and column address input to enable writing into or reading out of data at said row and column location ;
a plurality of serial access memory means each selectively accessing a specified portion of the data of a row or column of said memory elements in parallel , and each of which is selectively directed to an output port through which said specified portion of data is serially output in synchronism with a clock signal ;
address latch means for receiving an external tap address indicating the first element of said specified portion of data to be output from one of said serial access memories ;
address counter means (storage unit, storage unit update module) for generating address signals to cause data to be serially output from a current one of said serial access memory means , wherein said address counter means is initialized with the address in said address latch means , and wherein said address counter means increments said address in response to said clock signal to access successive elements in said current one of said serial access memory means beginning with said first element corresponding to said tap address ;
and external signal means connected to said address counter means and operable prior to the accessing of all of the elements of said current one of said serial access memory means following said first element for causing said address counter means to load a new initial address from said address latch means , said new initial address indicating a first element in a different one (first set) of said serial access memory means , whereby said serial output from said current one of said serial access memory means terminates and serial output begins from said different one of said serial access memory means .

US5001672A
CLAIM 8 . A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns , each of said rows comprising a plurality of portions having equal numbers of columns , means for coupling the location corresponding to a row address input and a column address input to a first port , a serial access memory register having columns corresponding to the columns of one of said portions of said array , parallel transfer means for transferring data (remote storage device, corresponding storage unit) in parallel between a selected portion of a selected row of said memory array and said register , and means for transferring data serially between said register and a second port .